loadpatents
name:-0.010556936264038
name:-0.013434886932373
name:-0.0069169998168945
Richardson; Nicholas J. Patent Filings

Richardson; Nicholas J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Richardson; Nicholas J..The latest application filed is for "estimating an error rate associated with memory".

Company Profile
5.25.15
  • Richardson; Nicholas J. - San Diego CA
  • Richardson; Nicholas J. - La Jolla CA
  • Richardson; Nicholas J. - Tempe AZ
  • Richardson; Nicholas J. - LaJolla CA
  • Richardson; Nicholas J. - Scottsdale AZ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Estimating an error rate associated with memory
Grant 11,334,413 - Parthasarathy , et al. May 17, 2
2022-05-17
High throughput bit correction of data inside a word buffer for a product code decoder
Grant 10,846,175 - Parthasarathy , et al. November 24, 2
2020-11-24
Estimating An Error Rate Associated With Memory
App 20200159616 - Parthasarathy; Sivagnanam ;   et al.
2020-05-21
Updating reliability data
Grant 10,628,256 - Sharifi Tehrani , et al.
2020-04-21
Estimating an error rate associated with memory
Grant 10,572,338 - Parthasarathy , et al. Feb
2020-02-25
High Throughput Bit Correction Of Data Inside A Word Buffer For A Product Code Decoder
App 20190310912 - Parthasarathy; Sivagnanam ;   et al.
2019-10-10
Area Efficient Implementation Of A Product Code Error Correcting Code Decoder
App 20190312600 - Khayat; Patrick R. ;   et al.
2019-10-10
Area efficient implementation of a product code error correcting code decoder
Grant 10,439,648 - Khayat , et al. O
2019-10-08
Apparatuses and methods for layer-by-layer error correction
Grant 10,326,479 - Kaynak , et al.
2019-06-18
Updating Reliability Data
App 20190146866 - Sharifi Tehrani; Saeed ;   et al.
2019-05-16
Updating reliability data
Grant 10,191,804 - Tehrani , et al. Ja
2019-01-29
Estimating An Error Rate Associated With Memory
App 20180341546 - Parthasarathy; Sivagnanam ;   et al.
2018-11-29
Estimating an error rate associated with memory
Grant 10,061,643 - Parthasarathy , et al. August 28, 2
2018-08-28
Apparatuses And Methods For Layer-by-layer Error Correction
App 20180013451 - Kaynak; Mustafa N. ;   et al.
2018-01-11
Estimating An Error Rate Associated With Memory
App 20170097859 - Parthasarathy; Sivagnanam ;   et al.
2017-04-06
Updating reliability data with a variable node and check nodes
Grant 9,612,903 - Tehrani , et al. April 4, 2
2017-04-04
Estimating an error rate associated with memory
Grant 9,558,064 - Parthasarathy , et al. January 31, 2
2017-01-31
Updating Reliability Data
App 20160259686 - Tehrani; Saeed Sharifi ;   et al.
2016-09-08
Estimating An Error Rate Associated With Memory
App 20160218740 - Parthasarathy; Sivagnanam ;   et al.
2016-07-28
Updating Reliability Data
App 20140108883 - Tehrani; Saeed Sharifi ;   et al.
2014-04-17
Channel constrained code aware interleaver
Grant 8,055,973 - Garani , et al. November 8, 2
2011-11-08
Method and system for providing cascaded trie-based network packet search engines
Grant 7,895,213 - Richardson February 22, 2
2011-02-22
Channel Constrained Code Aware Interleaver
App 20100313083 - Garani; Shayan Srinivasa ;   et al.
2010-12-09
System and method for handling register dependency in a stack-based pipelined processor
Grant 7,496,734 - Richardson , et al. February 24, 2
2009-02-24
Method and system for providing cascaded trie-based network packet search engines
App 20080046428 - Richardson; Nicholas J.
2008-02-21
Method and system for providing cascaded trie-based network packet search engines
Grant 7,299,227 - Richardson November 20, 2
2007-11-20
Method and system for providing cascaded trie-based network packet search engines
App 20050055339 - Richardson, Nicholas J.
2005-03-10
Instruction fetch buffer stack fold decoder for generating foldable instruction status information
Grant 6,832,307 - Richardson December 14, 2
2004-12-14
Progressive instruction folding in a processor with fast instruction decode
App 20030046519 - Richardson, Nicholas J.
2003-03-06
Processor cache system with parity protection and method of operation
Grant 6,507,928 - Richardson January 14, 2
2003-01-14
Pipelined Non-blocking Level Two Cache System With Inherent Transaction Collision-avoidance
App 20020069326 - RICHARDSON, NICHOLAS J. ;   et al.
2002-06-06
Bus interface unit having multipurpose transaction buffer
Grant 6,205,506 - Richardson March 20, 2
2001-03-20
Method and apparatus for maintaining coherency for data transaction of CPU and bus device utilizing selective flushing mechanism
Grant 6,021,473 - Davis , et al. February 1, 2
2000-02-01
Combined consective byte update buffer
Grant 5,892,978 - Munguia , et al. April 6, 1
1999-04-06
Efficient soft reset in a personal computer
Grant 5,842,012 - Walker , et al. November 24, 1
1998-11-24
Dynamic arbitration system and method
Grant 5,619,661 - Crews , et al. April 8, 1
1997-04-08
Combination asynchronous cache system and automatic clock tuning device and method therefor
Grant 5,557,781 - Stones , et al. September 17, 1
1996-09-17
Cache memory support in an integrated memory system
Grant 5,454,107 - Lehman , et al. September 26, 1
1995-09-26
Coherent cache structures and methods
Grant 5,029,070 - McCarthy , et al. July 2, 1
1991-07-02
Coherent cache structures and methods
Grant 4,928,225 - McCarthy , et al. May 22, 1
1990-05-22

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