Reynolds; Bart

Patent Applications and Registrations

Patent applications and USPTO patent grants for Reynolds; Bart.The latest application filed is for "unified data model for heterogeneous integrated circuit".

Company Profile

2.18.0

Reynolds; Bart - Manzanita OR
Reynolds; Bart - Seattle WA
Reynolds; Bart - Campbell CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Unified data model for heterogeneous integrated circuit Grant 11,176,296 - Jha , et al. November 16, 2	2021-11-16
Programmable integrated circuits for emulation Grant 10,956,638 - Reynolds , et al. March 23, 2	2021-03-23
Programmable integrated circuits for emulation Grant 10,402,521 - Reynolds , et al. Sep	2019-09-03
Device graphics rendering for electronic designs Grant 10,331,837 - McEwen , et al.	2019-06-25
Constructing a model of a programmable logic device Grant 7,584,448 - Reynolds , et al. September 1, 2	2009-09-01
Determining networks of a tile module of a programmable logic device Grant 7,536,668 - Reynolds , et al. May 19, 2	2009-05-19
Comparing graphical and netlist connections of a programmable logic device Grant 7,472,370 - Reynolds , et al. December 30, 2	2008-12-30
Determining controlling pins for a tile module of a programmable logic device Grant 7,451,425 - Reynolds , et al. November 11, 2	2008-11-11
Determining reachable pins of a network of a programmable logic device Grant 7,451,420 - Reynolds , et al. November 11, 2	2008-11-11
Determining indices of configuration memory cell modules of a programmable logic device Grant 7,451,423 - Reynolds , et al. November 11, 2	2008-11-11
Determining programmable connections through a switchbox of a programmable logic device Grant 7,451,424 - Reynolds , et al. November 11, 2	2008-11-11
Method and apparatus for specifying addressability and bus connections in a logic design Grant 6,910,002 - Reynolds , et al. June 21, 2	2005-06-21
Programmable interface for a configurable system bus Grant 6,754,760 - Yee , et al. June 22, 2	2004-06-22
Method and apparatus for determining the width of a memory subsystem Grant 6,704,850 - Reynolds March 9, 2	2004-03-09
Bidirectional bus for use as an interconnect routing resource Grant 6,661,812 - Reynolds , et al. December 9, 2	2003-12-09
Method and apparatus for specifying address offsets and alignment in logic design Grant 6,658,547 - Reynolds , et al. December 2, 2	2003-12-02
Configurable processor system unit Grant 6,467,009 - Winegarden , et al. October 15, 2	2002-10-15
Structure and method for manually controlling automatic configuration in an integrated circuit logic block array Grant 5,448,493 - Topolewski , et al. September 5, 1	1995-09-05

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