Reyes; Alberto J.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Reyes; Alberto J..The latest application filed is for "system and method for correlated clock networks".
- Reyes; Alberto J. - Tempe AZ
- Reyes; Alberto J. - Phoenix AZ
| Patent | Date |
|---|---|
| System and method for correlated clock networks Grant 6,925,622 - Reyes August 2, 2 | 2005-08-02 |
| System and method for correlated clock networks App 20040064799 - Reyes, Alberto J. | 2004-04-01 |
| Architectural power estimation method and apparatus Grant 5,940,779 - Gaitonde , et al. August 17, 1 | 1999-08-17 |
| Method of selecting device threshold voltages for high speed and low power Grant 5,774,367 - Reyes , et al. June 30, 1 | 1998-06-30 |
| Method of generating power vectors for cell power dissipation simulation Grant 5,673,420 - Reyes , et al. September 30, 1 | 1997-09-30 |
| Low power flip-flop circuit and method thereof Grant 5,498,988 - Reyes , et al. March 12, 1 | 1996-03-12 |
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