Revilla; Juan G.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Revilla; Juan G..The latest application filed is for "method and apparatus for testing embedded cores".

Company Profile

0.16.11

Revilla; Juan G. - Austin TX
Revilla; Juan G. - Cary NC

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and apparatus for testing embedded cores Grant 7,568,141 - Menon , et al. July 28, 2	2009-07-28
Method and Apparatus for Testing Embedded Cores App 20080104466 - Menon; Sankaran M. ; et al.	2008-05-01
Variable width alignment engine for aligning instructions based on transition between buffers Grant 7,360,059 - Tomazin , et al. April 15, 2	2008-04-15
Method and apparatus for testing embedded cores Grant 7,313,739 - Menon , et al. December 25, 2	2007-12-25
Early exception detection Grant 7,272,705 - Revilla , et al. September 18, 2	2007-09-18
Method for extending the local memory address space of a processor Grant 7,174,429 - Revilla , et al. February 6, 2	2007-02-06
Peak power reduction when updating future file Grant 7,124,285 - Inoue , et al. October 17, 2	2006-10-17
Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanism Grant 7,082,516 - Tomazin , et al. July 25, 2	2006-07-25
Aligning instructions using a variable width instruction alignment engine App 20060149928 - Tomazin; Thomas ; et al.	2006-07-06
Method and apparatus for converting an external memory access into a local memory access in a processor core Grant 7,028,129 - Revilla , et al. April 11, 2	2006-04-11
Early exception detection App 20050223205 - Revilla, Juan G. ; et al.	2005-10-06
Early exception detection Grant 6,920,515 - Revilla , et al. July 19, 2	2005-07-19
Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit Grant 6,874,078 - Pechanek , et al. March 29, 2	2005-03-29
Processor reset and instruction fetches Grant 6,789,187 - Singh , et al. September 7, 2	2004-09-07
Merged array controller with processing element App 20040148488 - Pechanek, Gerald G. ; et al.	2004-07-29
Method and apparatus for testing embedded cores App 20040128596 - Menon, Sankaran M. ; et al.	2004-07-01
Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bit Grant 6,606,699 - Pechanek , et al. August 12, 2	2003-08-12
Method for extending the local memory address space of a processor App 20030126367 - Revilla, Juan G. ; et al.	2003-07-03
Method and apparatus for converting an external memory access into a local memory access in a processor core App 20030126345 - Revilla, Juan G. ; et al.	2003-07-03
Peak power reduction when updating future file App 20020144100 - Inoue, Ryo ; et al.	2002-10-03
Early exception detection App 20020144041 - Revilla, Juan G. ; et al.	2002-10-03
Extended processor reset App 20020078336 - Singh, Ravi P. ; et al.	2002-06-20
Merged array controller and processing element App 20010032303 - Pechanek, Gerald G. ; et al.	2001-10-18
Merged array controller and processing element Grant 6,219,776 - Pechanek , et al. April 17, 2	2001-04-17
Data processing system and method for providing memory access protection using transparent translation registers and default attribute bits Grant 5,623,636 - Revilla , et al. April 22, 1	1997-04-22
Method and apparatus for testing pin isolation for an integrated circuit in a low power mode of operation Grant 5,561,614 - Revilla , et al. October 1, 1	1996-10-01
Method and apparatus for testing a clock stopping/starting function of a low power mode in a data processor Grant 5,553,236 - Revilla , et al. September 3, 1	1996-09-03

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.