Restle; Phillip John

Patent Applications and Registrations

Patent applications and USPTO patent grants for Restle; Phillip John.The latest application filed is for "proactive voltage droop reduction and/or mitigation in a processor core".

Company Profile

9.20.19

Restle; Phillip John - Katonah NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Proactive Voltage Droop Reduction And/or Mitigation In A Processor Core App 20220164250 - Biran; Giora ; et al.	2022-05-26
Proactive voltage droop reduction and/or mitigation in a processor core Grant 11,275,644 - Biran , et al. March 15, 2	2022-03-15
Voltage Management Via On-chip Sensors App 20220075435 - Bose; Pradip ; et al.	2022-03-10
On-chip supply noise voltage reduction or mitigation using local detection loops Grant 11,073,884 - Bose , et al. July 27, 2	2021-07-27
Determining clock signal quality using a plurality of sensors Grant 10,666,415 - Restle , et al.	2020-05-26
Determining clock signal quality using a plurality of sensors Grant 10,652,006 - Restle , et al.	2020-05-12
Proactive Voltage Droop Reduction And/or Mitigation In A Processor Core App 20200110656 - Biran; Giora ; et al.	2020-04-09
Proactive voltage droop reduction and/or mitigation in a processor core Grant 10,552,250 - Biran , et al. Fe	2020-02-04
On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core Grant 10,333,520 - Bose , et al.	2019-06-25
Voltage Management Via On-chip Sensors App 20190146568 - Bose; Pradip ; et al.	2019-05-16
Proactive Voltage Droop Reduction And/or Mitigation In A Processor Core App 20190108087 - Biran; Giora ; et al.	2019-04-11
On-chip Supply Noise Voltage Reduction Or Mitigation Using Local Detection Loops In A Processor Core App 20190036530 - Bose; Pradip ; et al.	2019-01-31
On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core Grant 10,171,081 - Bose , et al. J	2019-01-01
Determining Clock Signal Quality Using A Plurality Of Sensors App 20180198595 - Restle; Phillip John ; et al.	2018-07-12
Determining Clock Signal Quality Using A Plurality Of Sensors App 20180198596 - Restle; Phillip John ; et al.	2018-07-12
Infrastructure for performance based chip-to-chip stacking Grant 9,251,913 - Carpenter , et al. February 2, 2	2016-02-02
Defect detection on characteristically capacitive circuit nodes Grant 8,860,425 - Pang , et al. October 14, 2	2014-10-14
Direct current circuit analysis based clock network design Grant 8,775,996 - Alpert , et al. July 8, 2	2014-07-08
Changing Resonant Clock Modes App 20140167832 - Bucelot; Thomas J. ; et al.	2014-06-19
Changing resonant clock modes Grant 8,736,342 - Bucelot , et al. May 27, 2	2014-05-27
Direct Current Circuit Analysis Based Clock Network Design App 20140143746 - Alpert; Charles Jay ; et al.	2014-05-22
Designing a robust power efficient clock distribution network Grant 8,677,305 - Alpert , et al. March 18, 2	2014-03-18
Designing A Robust Power Efficient Clock Distribution Network App 20130326456 - Alpert; Charles Jay ; et al.	2013-12-05
Defect Detection on Characteristically Capacitive Circuit Nodes App 20130229189 - Pang; Liang-Teck ; et al.	2013-09-05
Infrastructure For Performance Based Chip-to-chip Stacking App 20120313647 - CARPENTER; GARY DALE ; et al.	2012-12-13
Bonding Controller Guided Assessment And Optimizationfor Chip-to-chip Stacking App 20120266125 - Carpenter; Gary Dale ; et al.	2012-10-18
Self-learning of the optimal power or performance operating point of a computer chip based on instantaneous feedback of present operating environment Grant 7,962,887 - Anderson , et al. June 14, 2	2011-06-14
Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique Grant 7,941,689 - Hwang , et al. May 10, 2	2011-05-10
Self-Learning of the Optimal Power or Performance Operating Point of a Computer Chip Based on Instantaneous Feedback of Present Operating Environment App 20090312848 - Anderson; Carl John ; et al.	2009-12-17
Minimizing Clock Uncertainty On Clock Distribution Networks Using A Multi-level De-skewing Technique App 20090237134 - Hwang; Charlie Chornglii ; et al.	2009-09-24
Method and apparatus for correcting duty cycle error in a clock distribution network App 20070229115 - Hwang; Charlie Chornglii ; et al.	2007-10-04
X-Y grid tree clock distribution network with tunable tree and grid networks Grant 6,311,313 - Camporese , et al. October 30, 2	2001-10-30
X-Y grid tree tuning method Grant 6,205,571 - Camporese , et al. March 20, 2	2001-03-20
Method of clock routing for semiconductor chips Grant 6,006,025 - Cook , et al. December 21, 1	1999-12-21

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