Restle; Phillip J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Restle; Phillip J..The latest application filed is for "mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors".

Company Profile

3.38.35

Restle; Phillip J. - Katonah NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors Grant 11,036,276 - Chuang , et al. June 15, 2	2021-06-15
Mitigation Of On-chip Supply Voltage Noise By Monitoring Slope Of Supply Voltage Based On Time-based Sensors App 20200019224 - Chuang; Pierce I-Jen ; et al.	2020-01-16
Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors Grant 10,437,311 - Chuang , et al. O	2019-10-08
Mitigation of on-chip supply voltage based on local and non-local (neighboring) cores' supply voltage information and decision Grant 10,261,561 - Chuang , et al.	2019-04-16
Increasing the resolution of on-chip measurement circuits Grant 10,145,892 - Franch , et al. De	2018-12-04
Sequenced pulse-width adjustment in a resonant clocking circuit Grant 10,141,915 - Bucelot , et al. Nov	2018-11-27
Mitigation Of On-chip Supply Voltage Based On Local And Non-local (neighboring) Cores' Supply Voltage Information And Decision. App 20180067541 - CHUANG; PIERCE I. ; et al.	2018-03-08
Mitigation Of On-chip Supply Voltage Noise By Monitoring Slope Of Supply Voltage Based On Time-based Sensors App 20180067532 - CHUANG; PIERCE I. ; et al.	2018-03-08
Increasing The Resolution Of On-chip Measurement Circuits App 20180052200 - FRANCH; ROBERT L. ; et al.	2018-02-22
Stitchable global clock for 3D chips Grant 9,800,232 - Franch , et al. October 24, 2	2017-10-24
Sequenced Pulse-width Adjustment In A Resonant Clocking Circuit App 20170207772 - Bucelot; Thomas J. ; et al.	2017-07-20
Sequenced pulse-width adjustment in a resonant clocking circuit Grant 9,705,479 - Bucelot , et al. July 11, 2	2017-07-11
Sequenced pulse-width adjustment in a resonant clocking circuit Grant 9,634,654 - Bucelot , et al. April 25, 2	2017-04-25
Pulse-drive resonant clock with on-the-fly mode change Grant 9,618,966 - Bucelot , et al. April 11, 2	2017-04-11
Tunable sector buffer for wide bandwidth resonant global clock distribution Grant 9,612,612 - Bucelot , et al. April 4, 2	2017-04-04
Pulse-drive resonant clock with on-the-fly mode change Grant 9,612,614 - Bucelot , et al. April 4, 2	2017-04-04
Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping Grant 9,575,119 - Franch , et al. February 21, 2	2017-02-21
Clock buffers with pulse drive capability for power efficiency Grant 9,571,100 - Bansal , et al. February 14, 2	2017-02-14
Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping Grant 9,568,548 - Franch , et al. February 14, 2	2017-02-14
Sequenced Pulse-width Adjustment In A Resonant Clocking Circuit App 20170040981 - Bucelot; Thomas J. ; et al.	2017-02-09
Sequenced Pulse-width Adjustment In A Resonant Clocking Circuit App 20170040987 - Bucelot; Thomas J. ; et al.	2017-02-09
Pulse-drive Resonant Clock With On-the-fly Mode Change App 20170031383 - Bucelot; Thomas J. ; et al.	2017-02-02
Pulse-drive Resonant Clock With On-the-fly Mode Change App 20170031384 - Bucelot; Thomas J. ; et al.	2017-02-02
Clock skew analysis and optimization Grant 9,494,968 - Restle , et al. November 15, 2	2016-11-15
Stitchable Global Clock For 3d Chips App 20160211833 - FRANCH; ROBERT L. ; et al.	2016-07-21
Stitchable global clock for 3D chips Grant 9,348,357 - Franch , et al. May 24, 2	2016-05-24
Clock Buffers With Pulse Drive Capability For Power Efficiency App 20160105177 - BANSAL; ADITYA ; et al.	2016-04-14
Clock buffers with pulse drive capability for power efficiency Grant 9,276,563 - Bansal , et al. March 1, 2	2016-03-01
Setting switch size and transition pattern in a resonant clock distribution system Grant 9,268,886 - Hibbeler , et al. February 23, 2	2016-02-23
Distributed phase detection for clock synchronization in multi-layer 3D stacks Grant 9,231,603 - Liu , et al. January 5, 2	2016-01-05
Stitchable Global Clock For 3d Chips App 20150378388 - FRANCH; ROBERT L. ; et al.	2015-12-31
Clock Buffers With Pulse Drive Capability For Power Efficiency App 20150365076 - BANSAL; ADITYA ; et al.	2015-12-17
Distributed Phase Detection For Clock Synchronization In Multi-layer 3d Stacks App 20150280722 - Liu; Yong ; et al.	2015-10-01
Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution App 20150234422 - Bucelot; Thomas J. ; et al.	2015-08-20
Tunable sector buffer for wide bandwidth resonant global clock distribution Grant 9,058,130 - Bucelot , et al. June 16, 2	2015-06-16
Wide bandwidth resonant global clock distribution Grant 9,054,682 - Bucelot , et al. June 9, 2	2015-06-09
Setting switch size and transition pattern in a resonant clock distribution system Grant 8,887,118 - Hibbeler , et al. November 11, 2	2014-11-11
Wiring-optimal method to route high performance clock nets satisfying electrical and reliability constraints Grant 8,863,066 - Kozhaya , et al. October 14, 2	2014-10-14
Setting switch size and transition pattern in a resonant clock distribution system Grant 8,850,373 - Hibbeler , et al. September 30, 2	2014-09-30
Setting Switch Size And Transition Pattern In A Resonant Clock Distribution System App 20140240021 - HIBBELER; Jason D. ; et al.	2014-08-28
Setting Switch Size And Transition Pattern In A Resonant Clock Distribution System App 20140245250 - HIBBELER; Jason D. ; et al.	2014-08-28
Setting Switch Size And Transition Pattern In A Resonant Clock Distribution System App 20140245244 - HIBBELER; Jason D. ; et al.	2014-08-28
Wide Bandwidth Resonant Global Clock Distribution App 20140218087 - Bucelot; Thomas J. ; et al.	2014-08-07
Tunable Sector Buffer for Wide Bandwidth Resonant Global Clock Distribution App 20140223210 - Bucelot; Thomas J. ; et al.	2014-08-07
Clock Skew Analysis And Optimization App 20140201561 - Restle; Phillip J. ; et al.	2014-07-17
Variable resistance switch for wide bandwidth resonant global clock distribution Grant 8,704,576 - Bucelot , et al. April 22, 2	2014-04-22
Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network Grant 8,525,569 - Bucelot , et al. September 3, 2	2013-09-03
Vertical power budgeting and shifting for three-dimensional integration Grant 8,516,426 - Bose , et al. August 20, 2	2013-08-20
Vertical Power Budgeting And Shifting For 3d Integration App 20130055185 - BOSE; PRADIP ; et al.	2013-02-28
Synchronizing Global Clocks In 3d Stacks Of Integrated Circuits By Shorting The Clock Network App 20130049827 - BUCELOT; THOMAS J. ; et al.	2013-02-28
Hindering Side-Channel Attacks in Integrated Circuits App 20120124669 - Carpenter; Gary D. ; et al.	2012-05-17
Duty cycle measurement circuit for measuring and maintaining balanced clock duty cycle Grant 7,961,559 - Dixon , et al. June 14, 2	2011-06-14
Duty Cycle Measurement Circuit For Measuring And Maintaining Balanced Clock Duty Cycle App 20090295449 - Dixon; Robert C. ; et al.	2009-12-03
Resonant tree driven clock distribution grid Grant 7,571,410 - Restle August 4, 2	2009-08-04
Hierarchical scalable high resolution digital programmable delay circuit Grant 7,456,671 - Hwang , et al. November 25, 2	2008-11-25
Duty Cycle Measurment Circuit For Measuring And Maintaining Balanced Clock Duty Cycle App 20080198700 - Franch; Robert L. ; et al.	2008-08-21
Method For Built In Self Test For Measuring Total Timing Uncertainty In A Digital Data Path App 20080198699 - Franch; Robert L. ; et al.	2008-08-21
Hierarchical Scalable High Resolution Digital Programmable Delay Circuit App 20080169857 - Hwang; Charlie C ; et al.	2008-07-17
Built in self test circuit for measuring total timing uncertainty in a digital data path Grant 7,400,555 - Franch , et al. July 15, 2	2008-07-15
Resonant Tree Driven Clock Distribution Grid App 20070209028 - Restle; Phillip J.	2007-09-06
Resonant tree driven clock distribution grid Grant 7,237,217 - Restle June 26, 2	2007-06-26
Duty Cycle Measurment Circuit For Measuring And Maintaining Balanced Clock Duty Cycle App 20070103141 - Dixon; Robert C. ; et al.	2007-05-10
Clock gated power supply noise compensation Grant 6,933,754 - Restle August 23, 2	2005-08-23
Resonant tree driven clock distribution grid App 20050114820 - Restle, Phillip J.	2005-05-26
Clock gated power supply noise compensation App 20050104646 - Restle, Phillip J.	2005-05-19
Built in self test circuit for measuring total timing uncertainty in a digital data path App 20050107970 - Franch, Robert L. ; et al.	2005-05-19
Alpha particle shield for integrated circuit Grant 6,531,759 - Wachnik , et al. March 11, 2	2003-03-11
Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation Grant 6,418,401 - Dansky , et al. July 9, 2	2002-07-09
Capacitive bend sensor Grant 5,610,528 - Neely , et al. March 11, 1	1997-03-11

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.