loadpatents
name:-0.036478996276855
name:-0.049121141433716
name:-0.0040848255157471
Reohr; William Robert Patent Filings

Reohr; William Robert

Patent Applications and Registrations

Patent applications and USPTO patent grants for Reohr; William Robert.The latest application filed is for "jtl-based superconducting logic arrays and fpgas".

Company Profile
5.52.32
  • Reohr; William Robert - Severna Park MD
  • Reohr; William Robert - Ridgefield CT US
  • Reohr; William Robert - Ridgefiled CT
  • Reohr; William Robert - Pleasantville NY
  • Reohr; William Robert - Chappaqua NY
  • Reohr; William Robert - Bronx NY
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
JTL-based superconducting logic arrays and FPGAS
Grant 10,756,738 - Reohr , et al. A
2020-08-25
Jtl-based Superconducting Logic Arrays And Fpgas
App 20200028512 - REOHR; WILLIAM ROBERT ;   et al.
2020-01-23
JTL-based superconducting logic arrays and FPGAs
Grant 10,447,278 - Reohr , et al. Oc
2019-10-15
Timing control in a quantum memory system
Grant 9,761,305 - Reohr , et al. September 12, 2
2017-09-12
Timing Control In A Quantum Memory System
App 20170229167 - REOHR; WILLIAM ROBERT ;   et al.
2017-08-10
Superconducting cell array logic circuit system
Grant 9,595,970 - Reohr , et al. March 14, 2
2017-03-14
Superconducting phase-controlled hysteretic magnetic Josephson junction JMRAM memory cell
Grant 9,520,181 - Miller , et al. December 13, 2
2016-12-13
Timing control in a quantum memory system
Grant 9,384,827 - Reohr , et al. July 5, 2
2016-07-05
Defect detection on characteristically capacitive circuit nodes
Grant 8,860,425 - Pang , et al. October 14, 2
2014-10-14
Enhanced data retention mode for dynamic memories
Grant 8,605,489 - Reohr , et al. December 10, 2
2013-12-10
Defect Detection on Characteristically Capacitive Circuit Nodes
App 20130229189 - Pang; Liang-Teck ;   et al.
2013-09-05
Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components
Grant 8,495,444 - Knebel , et al. July 23, 2
2013-07-23
Enhanced Data Retention Mode for Dynamic Memories
App 20130135941 - Reohr; William Robert ;   et al.
2013-05-30
High voltage word line driver
Grant 8,120,968 - Reohr , et al. February 21, 2
2012-02-21
Dynamic memory architecture employing passive expiration of data
Grant 8,020,073 - Emma , et al. September 13, 2
2011-09-13
High Voltage Word Line Driver
App 20110199837 - Reohr; William Robert ;   et al.
2011-08-18
Method and structure for asynchronous skip-ahead in synchronous pipelines
Grant 7,945,765 - Emma , et al. May 17, 2
2011-05-17
Memory sensing method and apparatus
Grant 7,920,434 - Meterelliyoz , et al. April 5, 2
2011-04-05
Memory Sensing Method and Apparatus
App 20100054057 - Meterelliyoz; Mesut ;   et al.
2010-03-04
Method And Structure For Asynchronous Skip-ahead In Synchronous Pipelines
App 20090198970 - Emma; Philip George ;   et al.
2009-08-06
Differential and hierarchical sensing for memory circuits
Grant 7,564,729 - Barth, Jr. , et al. July 21, 2
2009-07-21
Dynamic Memory Architecture Employing Passive Expiration Of Data
App 20090019341 - Emma; Philip George ;   et al.
2009-01-15
Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components
Grant 7,475,320 - Knebel , et al. January 6, 2
2009-01-06
Latency-aware Replacement System And Method For Cache Memories
App 20080313407 - Hu; Zhigang ;   et al.
2008-12-18
Frequency Modification Techniques That Adjust An Operating Frequency To Compensate For Aging Electronic Components
App 20080263383 - Knebel; Daniel R. ;   et al.
2008-10-23
Differential and Hierarchical Sensing for Memory Circuits
App 20080175085 - Barth; John Edward ;   et al.
2008-07-24
Differential and hierarchical sensing for memory circuits
Grant 7,382,672 - Barth, Jr. , et al. June 3, 2
2008-06-03
Enhanced sensing in a hierarchical memory architecture
Grant 7,336,553 - Reohr February 26, 2
2008-02-26
Dynamic memory architecture employing passive expiration of data
Grant 7,290,203 - Emma , et al. October 30, 2
2007-10-30
Differential and hierarchical sensing for memory circuits
Grant 7,286,385 - Barth, Jr. , et al. October 23, 2
2007-10-23
Latency-aware replacement system and method for cache memories
Grant 7,284,095 - Hu , et al. October 16, 2
2007-10-16
Differential and Hierarchical Sensing for Memory Circuits
App 20070223298 - Barth; John Edward JR. ;   et al.
2007-09-27
Enhanced sensing in a hierarchical memory architecture
Grant 7,257,042 - Reohr August 14, 2
2007-08-14
Enhanced Sensing In A Hierarchical Memory Architecture
App 20070183238 - Reohr; William Robert
2007-08-09
Enhanced Sensing In A Hierarchical Memory Architecture
App 20070159902 - Reohr; William Robert
2007-07-12
Differential and hierarchical sensing for memory circuits
App 20070025170 - Barth; John Edward JR. ;   et al.
2007-02-01
Method and apparatus for superimposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals
Grant 7,158,604 - Emma , et al. January 2, 2
2007-01-02
Location-based placement algorithms for set associative cache memory
Grant 7,093,075 - Reohr , et al. August 15, 2
2006-08-15
Dynamic memory architecture employing passive expiration of data
App 20060107090 - Emma; Philip George ;   et al.
2006-05-18
Cross-point memory architecture with improved selectivity
Grant 7,046,550 - Reohr , et al. May 16, 2
2006-05-16
Latency-aware replacement system and method for cache memories
App 20060041720 - Hu; Zhigang ;   et al.
2006-02-23
Magnetic random access memory using memory cells with rotated magnetic storage elements
Grant 6,975,555 - Lu , et al. December 13, 2
2005-12-13
Random access memory having an adaptable latency
Grant 6,961,276 - Atallah , et al. November 1, 2
2005-11-01
Current sense amplifier
Grant 6,946,882 - Gogl , et al. September 20, 2
2005-09-20
Memory array employing single three-terminal non-volatile storage elements
Grant 6,894,916 - Reohr , et al. May 17, 2
2005-05-17
Location-based placement algorithms for set associative cache memory
App 20050102475 - Reohr, William Robert ;   et al.
2005-05-12
Magnetic random access memory using memory cells with rotated magnetic storage elements
App 20050094445 - Lu, Yu ;   et al.
2005-05-05
Random access memory having an adaptable latency
App 20050063211 - Atallah, Francois Ibrahim ;   et al.
2005-03-24
Frequency modification techniques that adjust an operating frequency to compensate for aging electronic components
App 20050043910 - Knebel, Daniel R. ;   et al.
2005-02-24
Magnetic Random Access Memory Using Memory Cells With Rotated Magnetic Storage Elements
App 20040240266 - Lu, Yu ;   et al.
2004-12-02
Segmented Word Line Architecture For Cross Point Magnetic Random Access Memory
App 20040240265 - Lu, Yu ;   et al.
2004-12-02
Segmented word line architecture for cross point magnetic random access memory
Grant 6,816,405 - Lu , et al. November 9, 2
2004-11-09
Magnetic random access memory using memory cells with rotated magnetic storage elements
Grant 6,816,431 - Lu , et al. November 9, 2
2004-11-09
Architecture for high-speed magnetic memories
Grant 6,778,431 - Gogl , et al. August 17, 2
2004-08-17
Write circuit for a magnetic random access memory
Grant 6,778,429 - Lu , et al. August 17, 2
2004-08-17
Current sense amplifier
App 20040120200 - Gogl, Dietmar ;   et al.
2004-06-24
Architecture For High-speed Magnetic Memories
App 20040114439 - Gogl, Dietmar ;   et al.
2004-06-17
Non-volatile memory using ferroelectric gate field-effect transistors
Grant 6,744,087 - Misewich , et al. June 1, 2
2004-06-01
Non-volatile Memory Using Ferroelectric Gate Field-effect Transistors
App 20040061153 - Misewich, James A. ;   et al.
2004-04-01
Memory array employing single three-terminal non-volatile storage elements
App 20040062075 - Reohr, William Robert ;   et al.
2004-04-01
Select line architecture for magnetic random access memories
Grant 6,490,217 - DeBrosse , et al. December 3, 2
2002-12-03
Select Line Architecture For Magnetic Random Access Memories
App 20020176272 - DeBrosse, John Kenneth ;   et al.
2002-11-28
Data-dependent field compensation for writing magnetic random access memories
Grant 6,404,671 - Reohr , et al. June 11, 2
2002-06-11
Restore tracking system for DRAM
Grant 6,389,505 - Emma , et al. May 14, 2
2002-05-14
Segmented write line architecture for writing magnetic random access memories
Grant 6,335,890 - Reohr , et al. January 1, 2
2002-01-01
Interconnection network for connecting memory cells to sense amplifiers
Grant 6,269,040 - Reohr , et al. July 31, 2
2001-07-31
Bidirectional data transfer path having increased bandwidth
Grant 6,242,950 - Bozso , et al. June 5, 2
2001-06-05
Embedded thermal conductors for semiconductor chips
Grant 6,100,199 - Joshi , et al. August 8, 2
2000-08-08
Method and apparatus for transposing differential signals onto a set of binary signals to increase the information-carrying capacity of the original set of signals
Grant 6,038,260 - Emma , et al. March 14, 2
2000-03-14
Method for reducing power consumption in a set associative cache memory system
Grant 6,021,461 - Dhong , et al. February 1, 2
2000-02-01
Embedded thermal conductors for semiconductor chips
Grant 5,955,781 - Joshi , et al. September 21, 1
1999-09-21
Precharged bit decoder and sense amplifier with integrated latch usable in pipelined memories
Grant 5,783,949 - Reohr , et al. July 21, 1
1998-07-21

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed