| Patent | Date |
|---|
Distributed on-chip debug triggering with allocated bus lines
Grant 9,442,815 - Nixon , et al. September 13, 2 | 2016-09-13 |
Method and apparatus for on-chip debugging
Grant 9,129,061 - Nixon , et al. September 8, 2 | 2015-09-08 |
Debug state machines and methods of their operation
Grant 9,037,911 - Rentschler , et al. May 19, 2 | 2015-05-19 |
Multiple clock domain debug capability
Grant 8,959,398 - Nixon , et al. February 17, 2 | 2015-02-17 |
Correlating traces in a computing system
Grant 8,935,574 - Bedwell , et al. January 13, 2 | 2015-01-13 |
Multiple clock domain tracing
Grant 8,832,500 - Nixon , et al. September 9, 2 | 2014-09-09 |
Distributed On-chip Debug Triggering
App 20140122929 - Nixon; Scott P. ; et al. | 2014-05-01 |
Debug state machine cross triggering
Grant 8,683,265 - Rentschler , et al. March 25, 2 | 2014-03-25 |
Multiple Clock Domain Debug Capability
App 20140053027 - Nixon; Scott P. ; et al. | 2014-02-20 |
Debugging Multiple Exclusive Sequences Using Dsm Context Switches
App 20140053036 - Nixon; Scott P. ; et al. | 2014-02-20 |
Multiple Clock Domain Tracing
App 20140047262 - Nixon; Scott P. ; et al. | 2014-02-13 |
Method And Apparatus For On-chip Debugging
App 20140032801 - Nixon; Scott P. ; et al. | 2014-01-30 |
Correlating Traces In A Computing System
App 20130159780 - Bedwell; Ryan D. ; et al. | 2013-06-20 |
Debug State Machine Cross Triggering
App 20120150474 - Rentschler; Eric M. ; et al. | 2012-06-14 |
Debug State Machine Cross Triggering
App 20120146658 - Rentschler; Eric M. ; et al. | 2012-06-14 |
Debug State Machines And Methods Of Their Operation
App 20120151263 - RENTSCHLER; Eric M. ; et al. | 2012-06-14 |
Synchronizing link delay measurement over serial links
Grant 7,533,285 - Naffziger , et al. May 12, 2 | 2009-05-12 |
Mirrored computer memory on split bus
Grant 7,506,130 - Emmot , et al. March 17, 2 | 2009-03-17 |
Repeatability over communication links
Grant 7,289,587 - Rentschler , et al. October 30, 2 | 2007-10-30 |
Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe pad
Grant 7,103,793 - Rentschler , et al. September 5, 2 | 2006-09-05 |
Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of data
Grant 7,103,790 - Rentschler , et al. September 5, 2 | 2006-09-05 |
Memory controller to communicate with memory devices that are associated with differing data/strobe ratios
Grant 6,990,562 - Rentschler , et al. January 24, 2 | 2006-01-24 |
Synchronizing link delay measurement over serial links
App 20050238127 - Naffziger, Samuel D. ; et al. | 2005-10-27 |
Repeatability over communication links
App 20050240698 - Rentschler, Eric M. ; et al. | 2005-10-27 |
Memory controller receiver circuitry with tri-state noise immunity
Grant 6,889,335 - Hargis , et al. May 3, 2 | 2005-05-03 |
Memory controller to communicate with memory devices that are associated with differing data/strobe ratios
App 20040158688 - Rentschler, Eric M. ; et al. | 2004-08-12 |
Memory controller with 1X/MX read capability
App 20040133757 - Rentschler, Eric M. ; et al. | 2004-07-08 |
Memory controller with 1x/Mx write capability
App 20040088512 - Rentschler, Eric M. ; et al. | 2004-05-06 |
Memory controller with 1X/MX write capability
Grant 6,678,811 - Rentschler , et al. January 13, 2 | 2004-01-13 |
Mirrored computer memory on split bus
App 20030221059 - Emmot, Darel N. ; et al. | 2003-11-27 |
Mirrored computer memory on single bus
App 20030221058 - Rentschler, Eric M. ; et al. | 2003-11-27 |
Memory controller with 1.times./M.times. read capability
Grant 6,633,965 - Rentschler , et al. October 14, 2 | 2003-10-14 |
Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices
Grant 6,625,702 - Rentschler , et al. September 23, 2 | 2003-09-23 |
Memory controller receiver circuitry with tri-state noise immunity
App 20020172079 - Hargis, Jeffrey G. ; et al. | 2002-11-21 |
Memory controller with 1X/MX read capability
App 20020147892 - Rentschler, Eric M. ; et al. | 2002-10-10 |
Memory controller with 1X/MX write capability
App 20020147896 - Rentschler, Eric M. ; et al. | 2002-10-10 |
Memory controller with support for memory modules comprised of non-homogeneous data width RAM devices
App 20020147898 - Rentschler, Eric M. ; et al. | 2002-10-10 |
Mechanism For Implementing Bus Locking With A Mixed Architecture
App 20020038398 - MORRISON, JOHN A. ; et al. | 2002-03-28 |
Caching and coherency control of multiple geometry accelerators in a computer graphics system
Grant 5,969,726 - Rentschler , et al. October 19, 1 | 1999-10-19 |
Computer graphics system utilizing parallel processing for enhanced performance
Grant 5,821,950 - Rentschler , et al. October 13, 1 | 1998-10-13 |
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