Ren; Kaiyu
Patent Applications and Registrations
Patent applications and USPTO patent grants for Ren; Kaiyu.The latest application filed is for "functional failure analysis techniques for programmable integrated circuits".
- Ren; Kaiyu - San Jose CA
| Patent | Date |
|---|---|
| Functional failure analysis techniques for programmable integrated circuits Grant 7,685,485 - Vo , et al. March 23, 2 | 2010-03-23 |
| Bit error rate tester implemented in a programmable logic device Grant 7,194,666 - Wong , et al. March 20, 2 | 2007-03-20 |
| Functional failure analysis techniques for programmable integrated circuits App 20050022085 - Vo, Binh ; et al. | 2005-01-27 |
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