Reiss; Matthew M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Reiss; Matthew M..The latest application filed is for "stress reduction in flip-chip pbga packaging by utilizing segmented chips and/or chip carriers".

Company Profile

0.4.4

Reiss; Matthew M. - Endwell NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers Grant 6,989,607 - Darbha , et al. January 24, 2	2006-01-24
Stress reduction in flip-chip PBGA packaging by utilizing segmented chips and/or chip carriers App 20040021205 - Darbha, Krishna ; et al.	2004-02-05
Method of forming an apparatus to reduce thermal fatigue stress on flip chip solder connections Grant 6,667,557 - Alcoe , et al. December 23, 2	2003-12-23
Method Of Forming An Apparatus To Reduce Thermal Fatigue Stress On Flip Chip Solder Connections App 20030210531 - Alcoe, David J. ; et al.	2003-11-13
Stress reduction in flip-chip PBGA packaging by utilizing segmented chip carries Grant 6,639,302 - Darbha , et al. October 28, 2	2003-10-28
Stress Reduction In Flip-chip Pbga Packaging By Utilizing Segmented Chip Carriers App 20030178649 - Darbha, Krishna ; et al.	2003-09-25
Apparatus to reduce thermal fatigue stress on flip chip solder connections Grant 6,570,259 - Alcoe , et al. May 27, 2	2003-05-27
Apparatus to reduce thermal fatigue stress on flip chip solder connections App 20020135063 - Alcoe, David J. ; et al.	2002-09-26

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