Reilly; Matthew H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Reilly; Matthew H..The latest application filed is for "computer system and method using efficient module and backplane tiling to interconnect computer nodes via a kautz-like digraph".

Company Profile

0.8.12

Reilly; Matthew H. - Stow MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for preventing deadlock in richly-connected multi-processor computer system using dynamic assignment of virtual channels Grant 7,773,618 - Leonard , et al. August 10, 2	2010-08-10
System and method for communicating on a richly connected multi-processor computer system using a pool of buffers for dynamic association with a virtual channel Grant 7,773,616 - Reilly , et al. August 10, 2	2010-08-10
System and method for arbitration for virtual channels to prevent livelock in a richly-connected multi-processor computer system Grant 7,773,617 - Godiwala , et al. August 10, 2	2010-08-10
Computer system and method using a kautz-like digraph to interconnect computer nodes and having control back channel between nodes Grant 7,751,344 - Leonard , et al. July 6, 2	2010-07-06
Computer system and method using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph Grant 7,660,270 - Leonard , et al. February 9, 2	2010-02-09
Computer system and method using efficient module and backplane tiling to interconnect computer nodes via a Kautz-like digraph App 20080126571 - Leonard; Judson S. ; et al.	2008-05-29
System and method for arbitration for virtual channels to prevent livelock in a richly-connected multi-processor computer system App 20080109586 - Godiwala; Nitin ; et al.	2008-05-08
Large scale multi-processor system with a link-level interconnect providing in-order packet delivery App 20080107116 - Godiwala; Nitin ; et al.	2008-05-08
Systems and methods for remote direct memory access to processor caches for RDMA reads and writes App 20080109604 - Reilly; Matthew H. ; et al.	2008-05-08
System and method for communicating on a richly connected multi-processor computer system using a pool of buffers for dynamic association with a virtual channel App 20080107105 - Reilly; Matthew H. ; et al.	2008-05-08
System and method for preventing deadlock in richly-connected multi-processor computer system using dynamic assignment of virtual channels App 20080107106 - Leonard; Judson S. ; et al.	2008-05-08
Large scale computing system with multi-lane mesochronous data transfers among computer nodes App 20080109672 - Godiwala; Nitin ; et al.	2008-05-08
Computer system and method using a kautz-like digraph to interconnect computer nodes and having control back channel between nodes App 20080109544 - Leonard; Judson S. ; et al.	2008-05-08
System and method of multi-core cache coherency App 20070168620 - Leonard; Judson S. ; et al.	2007-07-19
Method and system with multiple exception handlers in a processor Grant 6,925,552 - Reilly , et al. August 2, 2	2005-08-02
Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit App 20040073905 - Emer, Joel S. ; et al.	2004-04-15
Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers Grant 6,675,192 - Emer , et al. January 6, 2	2004-01-06
Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit App 20030105944 - Emer, Joel S. ; et al.	2003-06-05
Hardware efficient handling of instruction exceptions to limit adverse impact on performance App 20020194467 - Reilly, Matthew H. ; et al.	2002-12-19
Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit Grant 6,493,741 - Emer , et al. December 10, 2	2002-12-10

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