Regnier; Arnaud

Patent Applications and Registrations

Patent applications and USPTO patent grants for Regnier; Arnaud.The latest application filed is for "mos transistor spacers and method of manufacturing the same".

Company Profile

21.43.46

Regnier; Arnaud - Les Taillades FR
Regnier; Arnaud - Les Tallades FR
Regnier; Arnaud - Les Talliades FR
Regnier; Arnaud - Le Tholonet FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Device of physically unclonable function with transistors, and manufacturing method Grant 11,405,223 - La Rosa , et al. August 2, 2	2022-08-02
Integrated circuit with vertically structured capacitive element, and its fabricating process Grant 11,139,303 - Marzaki , et al. October 5, 2	2021-10-05
Integrated circuit with vertically structured capacitive element, and its fabricating process Grant 11,081,488 - Marzaki , et al. August 3, 2	2021-08-03
Mos Transistor Spacers And Method Of Manufacturing The Same App 20210175346 - REGNIER; Arnaud ; et al.	2021-06-10
Co-integrated vertically structured capacitive element and fabrication process Grant 11,004,785 - Marzaki , et al. May 11, 2	2021-05-11
Structure and method of forming a semiconductor device Grant 10,971,633 - La Rosa , et al. April 6, 2	2021-04-06
Integrated filler capacitor cell device and corresponding manufacturing method Grant 10,943,862 - Marzaki , et al. March 9, 2	2021-03-09
Structure and Method of Forming a Semiconductor Device App 20210066510 - La Rosa; Francesco ; et al.	2021-03-04
Co-integrated Vertically Structured Capacitive Element And Fabrication Process App 20210057329 - MARZAKI; Abderrezak ; et al.	2021-02-25
Method of manufacturing MOS transistor spacers Grant 10,930,757 - Regnier , et al. February 23, 2	2021-02-23
Integrated Circuit With Vertically Structured Capacitive Element, And Its Fabricating Process App 20210005613 - MARZAKI; Abderrezak ; et al.	2021-01-07
Integrated Circuit With Vertically Structured Capacitive Element, And Its Fabricating Process App 20210005612 - MARZAKI; Abderrezak ; et al.	2021-01-07
Integrated circuit with vertically structured capacitive element, and its fabricating process Grant 10,818,669 - Marzaki , et al. October 27, 2	2020-10-27
Method for programming a split-gate memory cell and corresponding memory device Grant 10,796,763 - La Rosa , et al. October 6, 2	2020-10-06
Compact non-volatile memory device of the type with charge trapping in a dielectric interface Grant 10,790,293 - La Rosa , et al. September 29, 2	2020-09-29
Integrated circuit with improved resistive region Grant 10,770,357 - Froment , et al. Sep	2020-09-08
Device Of Physically Unclonable Function With Transistors, And Manufacturing Method App 20200274722 - La Rosa; Francesco ; et al.	2020-08-27
Memory cell comprising non-self-aligned horizontal and vertical control gates Grant 10,686,046 - La Rosa , et al.	2020-06-16
Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device Grant 10,541,270 - La Rosa , et al. Ja	2020-01-21
Compact Non-volatile Memory Device Of The Type With Charge Trapping In A Dielectric Interface App 20190371805 - La Rosa; Francesco ; et al.	2019-12-05
Memory Cell Comprising Non-self-aligned Horizontal And Vertical Control Gates App 20190341462 - LA ROSA; Francesco ; et al.	2019-11-07
Compact non-volatile memory device of the type with charge trapping in a dielectric interface Grant 10,438,960 - La Rosa , et al. O	2019-10-08
Integrated Circuit With Improved Resistive Region App 20190287862 - FROMENT; Benoit ; et al.	2019-09-19
Memory cell comprising non-self-aligned horizontal and vertical control gates Grant 10,403,730 - La Rosa , et al. Sep	2019-09-03
Method For Programming A Split-gate Memory Cell And Corresponding Memory Device App 20190237141 - LA ROSA; Francesco ; et al.	2019-08-01
Integrated circuit with improved resistive region Grant 10,354,926 - Froment , et al. July 16, 2	2019-07-16
Integrated Filler Capacitor Cell Device And Corresponding Manufacturing Method App 20190214341 - MARZAKI; Abderrezak ; et al.	2019-07-11
Mos Transistor Spacers And Method Of Manufacturing The Same App 20190207014 - REGNIER; Arnaud ; et al.	2019-07-04
Method for Forming a PN Junction and Associated Semiconductor Device App 20190067309 - La Rosa; Francesco ; et al.	2019-02-28
Integrated Circuit With Vertically Structured Capacitive Element, And Its Fabricating Process App 20190067291 - MARZAKI; Abderrezak ; et al.	2019-02-28
Vertical memory cell with non-self-aligned floating drain-source implant Grant 10,192,999 - Mantelli , et al. Ja	2019-01-29
Method for forming a PN junction and associated semiconductor device Grant 10,147,733 - La Rosa , et al. De	2018-12-04
Method For Fabricating An Array Of Diodes, In Particular For A Non-volatile Memory, And Corresponding Device App 20180294313 - La Rosa; Francesco ; et al.	2018-10-11
Integrated Circuit With Improved Resistive Region App 20180247874 - Froment; Beno t ; et al.	2018-08-30
Memory Cell Comprising Non-self-aligned Horizontal And Vertical Control Gates App 20180197963 - LA ROSA; Francesco ; et al.	2018-07-12
Method for fabricating an array of diodes, in particular for a non-volatile memory, and corresponding device Grant 10,002,906 - La Rosa , et al. June 19, 2	2018-06-19
Compact Non-volatile Memory Device Of The Type With Charge Trapping In A Dielectric Interface App 20180151584 - La Rosa; Francesco ; et al.	2018-05-31
Vertical Memory Cell With Non-self-aligned Floating Drain-source Implant App 20180145183 - MANTELLI; Marc ; et al.	2018-05-24
Twin memory cell interconnection structure Grant 9,941,012 - La Rosa , et al. April 10, 2	2018-04-10
Memory cell comprising non-self-aligned horizontal and vertical control gates Grant 9,941,369 - La Rosa , et al. April 10, 2	2018-04-10
Vertical memory cell with non-self-aligned floating drain-source implant Grant 9,876,122 - Mantelli , et al. January 23, 2	2018-01-23
Method For Fabricating An Array Of Diodes, In Particular For A Non-volatile Memory, And Corresponding Device App 20170352703 - La Rosa; Francesco ; et al.	2017-12-07
Method for Forming a PN Junction and Associated Semiconductor Device App 20170345836 - La Rosa; Francesco ; et al.	2017-11-30
Read performance of a non-volatile memory device, in particular a non-volatile memory device with buried selection transistor Grant 9,825,186 - La Rosa , et al. November 21, 2	2017-11-21
Read Performance Of A Non-volatile Memory Device, In Particular A Non-volatile Memory Device With Buried Selection Transistor App 20170278577 - La Rosa; Francesco ; et al.	2017-09-28
Memory cell having a vertical selection gate formed in an FDSOI substrate Grant 9,691,866 - Regnier , et al. June 27, 2	2017-06-27
Twin Memory Cell Interconnection Structure App 20170178733 - LA ROSA; Francesco ; et al.	2017-06-22
Integrated circuit protected from short circuits caused by silicide Grant 9,666,484 - Regnier , et al. May 30, 2	2017-05-30
Individually read-accessible twin memory cells Grant 9,653,470 - La Rosa , et al. May 16, 2	2017-05-16
Twin memory cell interconnection structure Grant 9,627,068 - La Rosa , et al. April 18, 2	2017-04-18
Dual non-volatile memory cell comprising an erase transistor Grant 9,613,709 - La Rosa , et al. April 4, 2	2017-04-04
Vertical Memory Cell With Non-self-aligned Floating Drain-source Implant App 20170084749 - MANTELLI; Marc ; et al.	2017-03-23
Dual Non-volatile Memory Cell Comprising An Erase Transistor App 20170011804 - La Rosa; Francesco ; et al.	2017-01-12
Vertical memory cell with non-self-aligned floating drain-source implant Grant 9,543,311 - Mantelli , et al. January 10, 2	2017-01-10
Memory Cell Having A Vertical Selection Gate Formed In An Fdsoi Substrate App 20160372561 - Regnier; Arnaud ; et al.	2016-12-22
Twin Memory Cell Interconnection Structure App 20160336070 - La Rosa; Francesco ; et al.	2016-11-17
Dual non-volatile memory cell comprising an erase transistor Grant 9,484,107 - La Rosa , et al. November 1, 2	2016-11-01
Memory Cell Comprising Non-self-aligned Horizontal And Vertical Control Gates App 20160308011 - LA ROSA; Francesco ; et al.	2016-10-20
Memory cell having a vertical selection gate formed in an FDSOI substrate Grant 9,461,129 - Regnier , et al. October 4, 2	2016-10-04
Method for programming a non-volatile memory cell comprising a shared select transistor gate Grant 9,443,598 - La Rosa , et al. September 13, 2	2016-09-13
Memory cell comprising non-self-aligned horizontal and vertical control gates Grant 9,406,686 - La Rosa , et al. August 2, 2	2016-08-02
Memory Cell Having A Vertical Selection Gate Formed In An Fdsoi Substrate App 20160181265 - Regnier; Arnaud ; et al.	2016-06-23
Method for biasing an embedded source plane of a non-volatile memory having vertical select gates Grant 9,368,215 - La Rosa , et al. June 14, 2	2016-06-14
Method For Biasing An Embedded Source Plane Of A Non-volatile Memory Having Vertical Select Gates App 20160071598 - La Rosa; Francesco ; et al.	2016-03-10
Hot-carrier injection programmable memory and method of programming such a memory Grant 9,224,482 - La Rosa , et al. December 29, 2	2015-12-29
Dual Non-volatile Memory Cell Comprising An Erase Transistor App 20150348640 - La Rosa; Francesco ; et al.	2015-12-03
Method For Programming A Non-volatile Memory Cell Comprising A Shared Select Transistor Gate App 20150348635 - La Rosa; Francesco ; et al.	2015-12-03
Individually Read-accessible Twin Memory Cells App 20150348981 - La Rosa; Francesco ; et al.	2015-12-03
Integrated Circuit Protected From Short Circuits Caused By Silicide App 20150325581 - Regnier; Arnaud ; et al.	2015-11-12
Vertical Memory Cell With Non-self-aligned Floating Drain-source Implant App 20150236031 - MANTELLI; Marc ; et al.	2015-08-20
Non-volatile memory with vertical selection transistors Grant 9,076,878 - La Rosa , et al. July 7, 2	2015-07-07
Hot-carrier Injection Programmable Memory And Method Of Programming Such A Memory App 20150117109 - LA ROSA; Francesco ; et al.	2015-04-30
Memory Cell Comprising Non-self-aligned Horizontal And Vertical Control Gates App 20150117117 - La Rosa; Francesco ; et al.	2015-04-30
Method of manufacturing a non-volatile memory Grant 9,012,961 - La Rosa , et al. April 21, 2	2015-04-21
Nonvolatile memory cells with a vertical selection gate of variable depth Grant 8,901,634 - La Rosa , et al. December 2, 2	2014-12-02
Method of reading and writing nonvolatile memory cells Grant 8,830,761 - La Rosa , et al. September 9, 2	2014-09-09
Integrated Circuit Protected From Short Circuits Caused By Silicide App 20140246720 - Regnier; Arnaud ; et al.	2014-09-04
Method Of Manufacturing A Non-volatile Memory App 20140191291 - La Rosa; Francesco ; et al.	2014-07-10
Adjustable resistor Grant 8,729,668 - Fornara , et al. May 20, 2	2014-05-20
Non-volatile Memory With Vertical Selection Transistors App 20140097481 - La Rosa; Francesco ; et al.	2014-04-10
Method Of Reading And Writing Nonvolatile Memory Cells App 20130229875 - La Rosa; Francesco ; et al.	2013-09-05
Nonvolatile Memory Cells With A Vertical Selection Gate Of Variable Depth App 20130228846 - LA ROSA; Francesco ; et al.	2013-09-05
Adjustable Resistor App 20130032926 - FORNARA; Pascal ; et al.	2013-02-07
Non-volatile reprogrammable memory Grant 7,675,106 - Bouchakour , et al. March 9, 2	2010-03-09
Floating-gate MOS transistor with double control gate Grant 7,242,621 - Mirabel , et al. July 10, 2	2007-07-10
Non-volatile reprogrammable memory App 20070069278 - Bouchakour; Rachid ; et al.	2007-03-29
Floating-gate MOS transistor with double control gate App 20050286303 - Mirabel, Jean-Michel ; et al.	2005-12-29

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