Rege; Satish L.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rege; Satish L..The latest application filed is for "disc drives divided into multiple logical containers".

Company Profile

0.11.2

Rege; Satish L. - Minneapolis MN
Rege; Satish L. - Groton MA
Rege; Satish L. - Somerset NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Log-structured block system and method Grant 6,895,468 - Rege , et al. May 17, 2	2005-05-17
Disc drives divided into multiple logical containers App 20030028719 - Rege, Satish L.	2003-02-06
Log-structured block system and method App 20020103983 - Rege, Satish L. ; et al.	2002-08-01
Method and apparatus for storage application programming interface for digital mass storage and retrieval based upon data object type or size and characteristics of the data storage device Grant 6,128,717 - Harrison , et al. October 3, 2	2000-10-03
Real time parser for data packets in a communications network Grant 5,805,808 - Hasani , et al. September 8, 1	1998-09-08
Symmetrically switched multimedia system Grant 5,612,897 - Rege March 18, 1	1997-03-18
Network adapter for interrupting host computer system in the event the host device driver is in both transmit and receive sleep states Grant 5,440,690 - Rege , et al. August 8, 1	1995-08-08
System for using three different methods to report buffer memory occupancy information regarding fullness-related and/or packet discard-related information Grant 5,390,299 - Rege , et al. February 14, 1	1995-02-14
Memory management for data transmission networks Grant 5,361,372 - Rege , et al. November 1, 1	1994-11-01
Monitor for packets on a communications network Grant 5,351,243 - Kalkunte , et al. September 27, 1	1994-09-27
Attribute based multiple data structures in host for network received traffic Grant 5,303,347 - Gagne , et al. April 12, 1	1994-04-12
Network adapter with high throughput data transfer circuit to optimize network data transfers, with host receive ring resource monitoring and reporting Grant 5,293,487 - Russo , et al. March 8, 1	1994-03-08
Error correcting circuits and methods for shift register type memories Grant 4,088,876 - Rege May 9, 1	1978-05-09

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