Reese; Robert James

Patent Applications and Registrations

Patent applications and USPTO patent grants for Reese; Robert James.The latest application filed is for "self-healing chip-to-chip interface".

Company Profile

0.10.7

Reese; Robert James - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-Healing Chip-to-Chip Interface App 20110010482 - Becker; Wiren Dale ; et al.	2011-01-13
Self-healing chip-to-chip interface Grant 7,813,266 - Becker , et al. October 12, 2	2010-10-12
Self-Healing Chip-to-Chip Interface App 20100085872 - Becker; Wiren Dale ; et al.	2010-04-08
Self-healing chip-to-chip interface Grant 7,362,697 - Becker , et al. April 22, 2	2008-04-22
Self-healing Chip-to-chip Interface App 20080074998 - BECKER; WIREN DALE ; et al.	2008-03-27
Methods, systems and media for functional simulation of noise and distortion on an I/O bus Grant 7,246,332 - Likovich, Jr. , et al. July 17, 2	2007-07-17
Methods, systems and media for functional simulation of noise and distortion on an I/O bus App 20060190857 - Likovich; Robert Brian JR. ; et al.	2006-08-24
Method and apparatus for interface failure survivability using error correction Grant 7,080,288 - Ferraiolo , et al. July 18, 2	2006-07-18
Method and apparatus for interface failure survivability using error correction App 20040216026 - Ferraiolo, Frank David ; et al.	2004-10-28
Self-healing chip-to-chip interface App 20040136319 - Becker, Wiren Dale ; et al.	2004-07-15
Phase detector Grant 6,762,626 - Dreps , et al. July 13, 2	2004-07-13
Method and apparatus for testing, characterizing and tuning a chip interface Grant 6,735,543 - Douskey , et al. May 11, 2	2004-05-11
Method and apparatus for testing, characterizing and tuning a chip interface App 20030101015 - Douskey, Steven Michael ; et al.	2003-05-29
Multiprocessor stalled store detection Grant 6,178,493 - Lenk , et al. January 23, 2	2001-01-23
System and method for indicating that a processor has prefetched data into a primary cache and not into a secondary cache Grant 5,758,119 - Mayfield , et al. May 26, 1	1998-05-26
Modified L1/L2 cache inclusion for aggressive prefetch Grant 5,740,399 - Mayfield , et al. April 14, 1	1998-04-14
Method and system for achieving atomic memory references in a multilevel cache data processing system Grant 5,706,464 - Moore , et al. January 6, 1	1998-01-06

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