Reece; William Robert
Patent Applications and Registrations
Patent applications and USPTO patent grants for Reece; William Robert.The latest application filed is for "dynamic weighting scheme for local cluster refinement".
- Reece; William Robert - Over GB
| Patent | Date |
|---|---|
| Dynamic weighting scheme for local cluster refinement Grant 11,188,702 - Jiang , et al. November 30, 2 | 2021-11-30 |
| Generate clock network using inverting integrated clock gate Grant 11,163,929 - Reece , et al. November 2, 2 | 2021-11-02 |
| Using negative-edge integrated clock gate in clock network Grant 11,132,490 - Jackson , et al. September 28, 2 | 2021-09-28 |
| Delay dependence in physically aware cell cloning Grant 10,990,721 - Reece , et al. April 27, 2 | 2021-04-27 |
| Modifying route topology to fix clock tree violations Grant 10,963,617 - Chapman , et al. March 30, 2 | 2021-03-30 |
| Multi-dimension clock gate design in clock tree synthesis Grant 10,963,618 - Farshidi , et al. March 30, 2 | 2021-03-30 |
| Route driven placement of fan-out clock drivers Grant 10,740,532 - Reece , et al. A | 2020-08-11 |
| Placement of cells in a multi-level routing tree Grant 10,402,533 - Reece , et al. Sep | 2019-09-03 |
| Region aware clustering Grant 10,402,522 - Viswanathan , et al. Sep | 2019-09-03 |
| Balanced scaled-load clustering Grant 10,318,693 - Viswanathan , et al. | 2019-06-11 |
| Clock cell library selection Grant 10,198,551 - Farshidi , et al. Fe | 2019-02-05 |
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