Redgrave; Jason Rupert

Patent Applications and Registrations

Patent applications and USPTO patent grants for Redgrave; Jason Rupert.The latest application filed is for "multi-functional execution lane for image processor".

Company Profile

44.68.69

Redgrave; Jason Rupert - Mountain View CA
Redgrave; Jason Rupert - Mountian View CA
Redgrave; Jason Rupert - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Synchronized data chaining using on-chip cache Grant 11,443,402 - Dodge , et al. September 13, 2	2022-09-13
Multi-functional Execution Lane For Image Processor App 20220206796 - Vasilyev; Artem ; et al.	2022-06-30
Multistage Collector For Outputs In Multiprocessor Systems App 20220101485 - McCombe; James Alexander ; et al.	2022-03-31
Multistage collector for outputs in multiprocessor systems Grant 11,227,362 - McCombe , et al. January 18, 2	2022-01-18
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register Grant 11,196,953 - Meixner , et al. December 7, 2	2021-12-07
Line buffer unit for image processor Grant 11,190,718 - Desai , et al. November 30, 2	2021-11-30
Two dimensional shift array for image processor Grant 11,153,464 - Shacham , et al. October 19, 2	2021-10-19
Energy efficient processor core architecture for image processor Grant 11,138,013 - Meixner , et al. October 5, 2	2021-10-05
Sheet generator for image processor Grant 11,140,293 - Meixner , et al. October 5, 2	2021-10-05
Way Partitioning For A System-level Cache App 20210255972 - Chamarty; Vinod ; et al.	2021-08-19
Shift register with reduced wiring complexity Grant 10,998,070 - Redgrave May 4, 2	2021-05-04
Convolutional Neural Network On Programmable Two Dimensional Image Processor App 20210004633 - Shacham; Ofer ; et al.	2021-01-07
Energy Efficient Processor Core Architecture for Image Processor App 20210004232 - Meixner; Albert ; et al.	2021-01-07
Way partitioning for a system-level cache Grant 10,884,959 - Chamarty , et al. January 5, 2	2021-01-05
Multistage Collector For Outputs In Multiprocessor Systems App 20200402199 - McCombe; James Alexander ; et al.	2020-12-24
Convolutional neural network on programmable two dimensional image processor Grant 10,789,505 - Shacham , et al. September 29, 2	2020-09-29
Virtual linebuffers for image signal processors Grant 10,791,284 - Zhu , et al. September 29, 2	2020-09-29
Multistage collector for outputs in multiprocessor systems Grant 10,783,605 - McCombe , et al. Sept	2020-09-22
Line Buffer Unit for Image Processor App 20200275040 - Desai; Neeti ; et al.	2020-08-27
Energy efficient processor core architecture for image processor Grant 10,754,654 - Meixner , et al. A	2020-08-25
System-level Cache App 20200257639 - A1	2020-08-13
Macro I/O unit for image processor Grant 10,733,956 - Meixner , et al.	2020-08-04
Circuit to perform dual input value absolute value and sum operation Grant 10,719,295 - Vasilyev , et al.	2020-07-21
Architecture for high performance, power efficient, programmable image processing Grant 10,719,905 - Zhu , et al.	2020-07-21
Synchronized Data Chaining Using On-chip Cache App 20200193554 - Dodge; Benjamin ; et al.	2020-06-18
Compiler managed memory for image processor Grant 10,685,422 - Meixner , et al.	2020-06-16
Sheet Generator For Image Processor App 20200186667 - Meixner; Albert ; et al.	2020-06-11
Macro I/O Unit for Image Processor App 20200160809 - Meixner; Albert ; et al.	2020-05-21
Shift Register with Reduced Wiring Complexity App 20200162705 - Redgrave; Jason Rupert	2020-05-21
Circuit To Perform Dual Input Value Absolute Value And Sum Operation App 20200159494 - Vasilyev; Artem ; et al.	2020-05-21
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register App 20200154072 - Meixner; Albert ; et al.	2020-05-14
Line buffer unit for image processor Grant 10,638,073 - Desai , et al.	2020-04-28
Virtual Linebuffers For Image Signal Processors App 20200120287 - Zhu; Qiuling ; et al.	2020-04-16
Sheet generator for image processor Grant 10,560,598 - Meixner , et al. Feb	2020-02-11
Convolutional neural network on programmable two dimensional image processor Grant 10,546,211 - Shacham , et al. Ja	2020-01-28
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register Grant 10,531,030 - Meixner , et al. J	2020-01-07
Virtual linebuffers for image signal processors Grant 10,516,833 - Zhu , et al. Dec	2019-12-24
Architecture For High Performance, Power Efficient, Programmable Image Processing App 20190378239 - Zhu; Qiuling ; et al.	2019-12-12
Macro I/O unit for image processor Grant 10,504,480 - Meixner , et al. Dec	2019-12-10
Two Dimensional Shift Array for Image Processor App 20190364174 - Shacham; Ofer ; et al.	2019-11-28
Shift register with reduced wiring complexity Grant 10,477,164 - Redgrave Nov	2019-11-12
Line Buffer Unit for Image Processor App 20190327433 - Desai; Neeti ; et al.	2019-10-24
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register App 20190327437 - Meixner; Albert ; et al.	2019-10-24
Architecture for high performance, power efficient, programmable image processing Grant 10,417,732 - Zhu , et al. Sept	2019-09-17
Two dimensional shift array for image processor Grant 10,397,450 - Shacham , et al. A	2019-08-27
Macro I/O unit for image processor Grant 10,380,969 - Meixner , et al. A	2019-08-13
Virtual Linebuffers For Image Signal Processors App 20190238758 - Zhu; Qiuling ; et al.	2019-08-01
Energy Efficient Processor Core Architecture for Image Processor App 20190220282 - Meixner; Albert ; et al.	2019-07-18
Multi-functional Execution Lane For Image Processor App 20190213006 - Vasilyev; Artem ; et al.	2019-07-11
Sheet Generator For Image Processor App 20190208075 - Meixner; Albert ; et al.	2019-07-04
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register Grant 10,334,194 - Meixner , et al.	2019-06-25
Compiler Managed Memory For Image Processor App 20190188824 - Meixner; Albert ; et al.	2019-06-20
Line buffer unit for image processor Grant 10,321,077 - Desai , et al.	2019-06-11
Multistage Collector For Outputs In Multiprocessor Systems App 20190172176 - McCombe; James Alexander ; et al.	2019-06-06
Shift register with reduced wiring complexity Grant 10,313,641 - Redgrave	2019-06-04
Compiler managed memory for image processor Grant 10,304,156 - Meixner , et al.	2019-05-28
Sheet generator for image processor Grant 10,291,813 - Meixner , et al.	2019-05-14
Sheet generator for image processor Grant 10,284,744 - Meixner , et al.	2019-05-07
Virtual linebuffers for image signal processors Grant 10,277,833 - Zhu , et al.	2019-04-30
Energy efficient processor core architecture for image processor Grant 10,275,253 - Meixner , et al.	2019-04-30
Multistage collector for outputs in multiprocessor systems Grant 10,242,426 - McCombe , et al.	2019-03-26
Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure Grant 10,216,487 - Meixner , et al. Feb	2019-02-26
Compiler managed memory for image processor Grant 10,204,396 - Meixner , et al. Feb	2019-02-12
Multi-functional execution lane for image processor Grant 10,185,560 - Vasilyev , et al. Ja	2019-01-22
Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure Grant 10,095,479 - Meixner , et al. October 9, 2	2018-10-09
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register App 20180234653 - Meixner; Albert ; et al.	2018-08-16
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register Grant 9,986,187 - Meixner , et al. May 29, 2	2018-05-29
Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register Grant 9,978,116 - Meixner , et al. May 22, 2	2018-05-22
Architecture for high performance, power efficient, programmable image processing Grant 9,965,824 - Zhu , et al. May 8, 2	2018-05-08
Convolutional Neural Network On Programmable Two Dimensional Image Processor App 20180005075 - Shacham; Ofer ; et al.	2018-01-04
Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register App 20180005346 - MEIXNER; Albert ; et al.	2018-01-04
Block Operations For An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register App 20180007302 - MEIXNER; Albert ; et al.	2018-01-04
Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and a Two-Dimensional Shift Register App 20180005347 - Meixner; Albert ; et al.	2018-01-04
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register App 20180007303 - Meixner; Albert ; et al.	2018-01-04
Convolutional Neural Network On Programmable Two Dimensional Image Processor App 20180005074 - SHACHAM; Ofer ; et al.	2018-01-04
Multi-functional execution lane for image processor Grant 9,830,150 - Vasilyev , et al. November 28, 2	2017-11-28
Two Dimensional Shift Array for Image Processor App 20170310855 - Shacham; Ofer ; et al.	2017-10-26
Compiler Managed Memory For Image Processor App 20170287105 - Meixner; Albert ; et al.	2017-10-05
Energy efficient processor core architecture for image processor Grant 9,772,852 - Meixner , et al. September 26, 2	2017-09-26
Two dimensional shift array for image processor Grant 9,769,356 - Shacham , et al. September 19, 2	2017-09-19
Architecture For High Performance, Power Efficient, Programmable Image Processing App 20170256021 - Zhu; Qiuling ; et al.	2017-09-07
Line Buffer Unit For Image Processor App 20170257585 - Desai; Neeti ; et al.	2017-09-07
Sheet Generator For Image Processor App 20170257515 - Meixner; Albert ; et al.	2017-09-07
Macro I/O Unit for Image Processor App 20170256230 - Meixner; Albert ; et al.	2017-09-07
Line buffer unit for image processor Grant 9,756,268 - Desai , et al. September 5, 2	2017-09-05
Energy Efficient Processor Core Architecture for Image Processor App 20170249153 - Meixner; Albert ; et al.	2017-08-31
Shift Register With Reduced Wiring Complexity App 20170251184 - Redgrave; Jason Rupert	2017-08-31
Macro I/O Unit for Image Processor App 20170249921 - MEIXNER; Albert ; et al.	2017-08-31
Compiler Managed Memory For Image Processor App 20170249717 - MEIXNER; Albert ; et al.	2017-08-31
Virtual linebuffers for image signal processors Grant 9,749,548 - Zhu , et al. August 29, 2	2017-08-29
Multi-functional Execution Lane For Image Processor App 20170242695 - Vasilyev; Artem ; et al.	2017-08-24
Virtual Image Processor Instruction Set Architecture (ISA) And Memory Model And Exemplary Target Hardware Having A Two-Dimensional Shift Array Structure App 20170242943 - Meixner; Albert ; et al.	2017-08-24
Virtual Linebuffers For Image Signal Processors App 20170206627 - Zhu; Qiuling ; et al.	2017-07-20
Multistage Collector For Outputs In Multiprocessor Systems App 20170178282 - McCombe; James Alexander ; et al.	2017-06-22
Multi-functional Execution Lane For Image Processor App 20170161064 - VASILYEV; Artem ; et al.	2017-06-08
Shift Register With Reduced Wiring Complexity App 20170163931 - REDGRAVE; Jason Rupert	2017-06-08
Variable-sized concurrent grouping for multiprocessing Grant 9,665,970 - Redgrave , et al. May 30, 2	2017-05-30
Multistage collector for outputs in multiprocessor systems Grant 9,595,074 - McCombe , et al. March 14, 2	2017-03-14
Virtual Image Processor Instruction Set Architecture (ISA) And Memory Model And Exemplary Target Hardware Having A Two-Dimensional Shift Array Structure App 20160313980 - Meixner; Albert ; et al.	2016-10-27
Energy Efficient Processor Core Architecture For Image Processor App 20160313999 - Meixner; Albert ; et al.	2016-10-27
Line Buffer Unit For Image Processor App 20160316157 - Desai; Neeti ; et al.	2016-10-27
Architecture For High Performance, Power Efficient, Programmable Image Processing App 20160314555 - Zhu; Qiuling ; et al.	2016-10-27
Two Dimensional Shift Array For Image Processor App 20160316107 - Shacham; Ofer ; et al.	2016-10-27
Sheet Generator For Image Processor App 20160316094 - Meixner; Albert ; et al.	2016-10-27
System and method of arbitrating access to interconnect Grant 9,407,578 - Richards , et al. August 2, 2	2016-08-02
Virtual Linebuffers For Image Signal Processors App 20160219225 - Zhu; Qiuling ; et al.	2016-07-28
Noise shaped interpolator and decimator apparatus and method Grant 9,325,488 - Norsworthy , et al. April 26, 2	2016-04-26
Noise Shaped Interpolator And Decimator Apparatus And Method App 20150341159 - Norsworthy; Steven R. ; et al.	2015-11-26
Noise shaped interpolator and decimator apparatus and method Grant 9,130,700 - Norsworthy , et al. September 8, 2	2015-09-08
Systems and methods for primitive intersection in ray tracing Grant 8,988,433 - Purcell , et al. March 24, 2	2015-03-24
Noise Shaped Interpolator And Decimator Apparatus And Method App 20140286467 - Norsworthy; Steven R. ; et al.	2014-09-25
System And Method of Arbitrating Access to Interconnect App 20140269760 - Richards; Joseph M. ; et al.	2014-09-18
Noise shaped interpolator and decimator apparatus and method Grant 8,744,032 - Norsworthy , et al. June 3, 2	2014-06-03
Graphics processor with non-blocking concurrent architecture Grant 8,692,834 - Peterson , et al. April 8, 2	2014-04-08
Graphics Processor with Non-Blocking Concurrent Architecture App 20130222402 - Peterson; Luke Tilman ; et al.	2013-08-29
Systems and methods for self-intersection avoidance in ray tracing Grant 8,441,482 - Ozdac , et al. May 14, 2	2013-05-14
Multistage Collector For Outputs In Multiprocessor Systems App 20130069960 - McCombe; James Alexander ; et al.	2013-03-21
Variable-sized Concurrent Grouping For Multiprocessing App 20120133654 - Redgrave; Jason Rupert ; et al.	2012-05-31
Noise Shaped Interpolator And Decimator Apparatus And Method App 20110299642 - Norsworthy; Steven R. ; et al.	2011-12-08
Systems And Methods For Primitive Intersection In Ray Tracing App 20110267347 - Purcell; Stephen ; et al.	2011-11-03
Noise shaped interpolator and decimator apparatus and method Grant 8,019,035 - Norsworthy , et al. September 13, 2	2011-09-13
Systems And Methods For Self-intersection Avoidance In Ray Tracing App 20110069067 - Ozdas; Cuneyt ; et al.	2011-03-24
Variable coder apparatus for resonant power conversion and method Grant 7,561,635 - Norsworthy , et al. July 14, 2	2009-07-14
Radio frequency digital-to-analog converter Grant 7,471,226 - Norsworthy , et al. December 30, 2	2008-12-30
Radio frequency envelope apparatus and method Grant 7,276,966 - Tham , et al. October 2, 2	2007-10-02
Radio frequency digital-to-analog converter App 20060244648 - Norsworthy; Steven R. ; et al.	2006-11-02
Radio frequency digital-to-analog converter Grant 7,116,253 - Norsworthy , et al. October 3, 2	2006-10-03
Noise shaped interpolator and decimator apparatus and method App 20050207480 - Norsworthy, Steven R. ; et al.	2005-09-22
Radio frequency digital-to-analog converter App 20050162294 - Norsworthy, Steven R. ; et al.	2005-07-28
Variable coder apparatus for resonant power conversion and method App 20050163232 - Norsworthy, Steven R. ; et al.	2005-07-28

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