loadpatents
name:-0.0088131427764893
name:-0.01349401473999
name:-0.0043511390686035
Reddy; Sagar V. Patent Filings

Reddy; Sagar V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Reddy; Sagar V..The latest application filed is for "dynamic transform in blockchain header validation".

Company Profile
3.9.5
  • Reddy; Sagar V. - Sunnyvale CA
  • Reddy; Sagar V. - Santa Clara CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Dynamic transform in blockchain header validation
Grant 11,296,866 - Rodriguez De Castro , et al. April 5, 2
2022-04-05
Cryptographic ASIC including circuitry-encoded transformation function
Grant 10,936,758 - Rodriguez De Castro , et al. March 2, 2
2021-03-02
Cryptographic ASIC with combined transformation and one-way functions
Grant 10,885,228 - Rodriguez De Castro , et al. January 5, 2
2021-01-05
Dynamic Transform In Blockchain Header Validation
App 20200228319 - Rodriguez De Castro; Edward L. ;   et al.
2020-07-16
Performance sensitive series string power supply
Grant 10,594,213 - Rodriguez De Castro , et al.
2020-03-17
Actively controlled series string power supply
Grant 10,591,966 - Rodriguez De Castro , et al.
2020-03-17
Cryptographic Asic With Combined Transformation And One-way Functions
App 20190325165 - Rodriguez De Castro; Edward L. ;   et al.
2019-10-24
Cryptographic Asic Including Circuitry-encoded Transformation Function
App 20190272393 - Rodriguez De Castro; Edward L. ;   et al.
2019-09-05
Cryptographic ASIC with combined transformation and one-way functions
Grant 10,372,943 - Rodriguez De Castro , et al.
2019-08-06
Cryptographic ASIC including circuitry-encoded transformation function
Grant 10,262,164 - Rodriguez De Castro , et al.
2019-04-16
Cryptographic Asic Including Circuitry-encoded Transformation Function
App 20170206382 - Rodriguez De Castro; Edward L. ;   et al.
2017-07-20
Mechanism for compensating for gate leakage in a memory
Grant 7,515,475 - Reddy April 7, 2
2009-04-07
Hybrid dual match line architecture for content addressable memories and other data structures
Grant 7,474,546 - Shastry , et al. January 6, 2
2009-01-06
Hybrid Dual Match Line Architecture For Content Addressable Memories And Other Data Structures
App 20080239778 - Shastry; Shashank ;   et al.
2008-10-02

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