Reddy; Dayanand K.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Reddy; Dayanand K..The latest application filed is for "delay-locked loop with built-in self-test of phase margin".
- Reddy; Dayanand K. - Farmington MN
- Reddy; Dayanand K. - Minneapolis MN
| Patent | Date |
|---|---|
| Delay-locked loop with built-in self-test of phase margin Grant 7,042,971 - Flanagan , et al. May 9, 2 | 2006-05-09 |
| System for measuring phase error between two clocks by using a plurality of phase latches with different respective delays Grant 6,636,979 - Reddy , et al. October 21, 2 | 2003-10-21 |
| Phase-locked loop with built-in self-test of phase margin and loop gain Grant 6,262,634 - Flanagan , et al. July 17, 2 | 2001-07-17 |
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