| Patent | Date |
|---|
Light modulator with integrated drive and control circuitry
Grant 7,375,874 - Novotny , et al. May 20, 2 | 2008-05-20 |
Integrated high speed switch router using a multiport architecture
Grant 7,251,249 - Nanduri , et al. July 31, 2 | 2007-07-31 |
Light modulator with integrated drive and control circuitry
Grant 7,075,701 - Novotny , et al. July 11, 2 | 2006-07-11 |
Light modulator with integrated drive and control circuitry
App 20060077531 - Novotny; Vlad ; et al. | 2006-04-13 |
MEMS devices monolithically integrated with drive and control circuitry
Grant 7,015,885 - Novotny , et al. March 21, 2 | 2006-03-21 |
MEMS devices monolithically integrated with drive and control circuitry
App 20050002079 - Novotny, Vlad J. ; et al. | 2005-01-06 |
Interconnect to plate contact/via arrangement for random access memory
App 20020081802 - Shrivastava, Ritu ; et al. | 2002-06-27 |
Semiconductor devices having cooperative mode option at assembly stage and method thereof
Grant 6,403,448 - Reddy June 11, 2 | 2002-06-11 |
DRAM cell having storage capacitor contact self-aligned to bit lines and word lines
App 20020053692 - Shrivastava, Ritu ; et al. | 2002-05-09 |
Shared memory graphics accelerator system
App 20010040581 - Reddy, Chitranjan N. | 2001-11-15 |
Shared memory graphics accelerator system
Grant 6,317,135 - Reddy November 13, 2 | 2001-11-13 |
Integrated high speed switch router using a multiport architecture
App 20010038636 - Nanduri, Bhanu ; et al. | 2001-11-08 |
Fusible link structure for semiconductor devices
Grant 6,025,214 - Reddy , et al. February 15, 2 | 2000-02-15 |
DRAM cell having storage capacitor contact self-aligned to bit lines and word lines
Grant 5,994,730 - Shrivastava , et al. November 30, 1 | 1999-11-30 |
Highly integrated low voltage SRAM array with low resistance Vss lines
Grant 5,831,315 - Kengeri , et al. November 3, 1 | 1998-11-03 |
Shared memory graphics accelerator system
Grant 5,712,664 - Reddy January 27, 1 | 1998-01-27 |
Dynamic random access memory cell having increased capacitance
Grant 5,701,264 - Shrivastava , et al. December 23, 1 | 1997-12-23 |
Random access memory having selective intra-bank fast activation of sense amplifiers
Grant 5,671,188 - Patel , et al. September 23, 1 | 1997-09-23 |
Reduced area word line driving circuit for random access memory
Grant 5,633,832 - Patel , et al. May 27, 1 | 1997-05-27 |
Burst random access memory employing sequenced banks of local tri-state drivers
Grant 5,617,555 - Patel , et al. April 1, 1 | 1997-04-01 |
Timing control circuit for synchronous static random access memory
Grant 5,559,752 - Stephens, Jr. , et al. September 24, 1 | 1996-09-24 |
Semiconductor electrode having improved grain structure and oxide growth properties
Grant 5,557,122 - Shrivastava , et al. September 17, 1 | 1996-09-17 |
Dual-port random access memory having reduced architecture
Grant 5,535,172 - Reddy , et al. July 9, 1 | 1996-07-09 |
High speed and hierarchical address transition detection circuit
Grant 5,448,529 - Reddy , et al. September 5, 1 | 1995-09-05 |
Hierarchical redundancy scheme for high density monolithic memories
Grant 5,377,146 - Reddy , et al. December 27, 1 | 1994-12-27 |
High-speed address transition detection circuit
Grant 5,306,958 - Reddy , et al. April 26, 1 | 1994-04-26 |
Monolithic fail bit memory
Grant 5,270,974 - Reddy December 14, 1 | 1993-12-14 |
Differential latch sense amplifier
Grant 5,231,318 - Reddy July 27, 1 | 1993-07-27 |
Dynamic memory with high speed nibble mode
Grant 4,567,579 - Patel , et al. January 28, 1 | 1986-01-28 |
Sequentially clocked substrate bias generator for dynamic memory
Grant 4,494,223 - Reddy , et al. January 15, 1 | 1985-01-15 |
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