| Patent | Date |
|---|
Apparatus for parallelizing serial instruction sequences and creating entry points into parallelized instruction sequences at places other than beginning of particular parallelized instruction sequence
Grant 5,412,784 - Rechtschaffen , et al. May 2, 1 | 1995-05-02 |
Self-scheduling parallel computer system and method
Grant 5,408,658 - Rechtschaffen , et al. April 18, 1 | 1995-04-18 |
Multi-prediction branch prediction mechanism
Grant 5,353,421 - Emma , et al. October 4, 1 | 1994-10-04 |
Self-parallelizing computer system and method
Grant 5,347,639 - Rechtschaffen , et al. September 13, 1 | 1994-09-13 |
Multiple sequence processor system
Grant 5,297,281 - Emma , et al. March 22, 1 | 1994-03-22 |
Method and apparatus for dynamic cache line sectoring in multiprocessor systems
Grant 5,291,442 - Emma , et al. March 1, 1 | 1994-03-01 |
Subroutine return through branch history table
Grant 5,276,882 - Emma , et al. January 4, 1 | 1994-01-04 |
Cache miss facility with stored sequences for data fetching
Grant 5,233,702 - Emma , et al. August 3, 1 | 1993-08-03 |
Methods and apparatus for insulating a branch prediction mechanism from data dependent branch table updates that result from variable test operand locations
Grant 5,210,831 - Emma , et al. May 11, 1 | 1993-05-11 |
Cache management for multi-processor systems utilizing bulk cross-invalidate
Grant 5,197,139 - Emma , et al. March 23, 1 | 1993-03-23 |
Data processing system with fast queue store interposed between store-through caches and a main memory
Grant 5,155,831 - Emma , et al. October 13, 1 | 1992-10-13 |
Pipeline processing apparatus for executing instructions in three streams, including branch stream pre-execution processor for pre-executing conditional branch instructions
Grant 4,991,080 - Emma , et al. February 5, 1 | 1991-02-05 |
Posting out-of-sequence fetches
Grant 4,991,090 - Emma , et al. February 5, 1 | 1991-02-05 |
Multiple branch analyzer for prefetching cache lines
Grant 4,943,908 - Emma , et al. July 24, 1 | 1990-07-24 |
High speed buffer store arrangement for quick wide transfer of data
Grant 4,823,259 - Aichelmann, Jr. , et al. April 18, 1 | 1989-04-18 |
Prefetching system for a cache having a second directory for sequentially accessed blocks
Grant 4,807,110 - Pomerene , et al. February 21, 1 | 1989-02-21 |
Apparatus and method for prefetching subblocks from a low speed memory to a high speed memory of a memory hierarchy depending upon state of replacing bit in the low speed memory
Grant 4,774,654 - Pomerene , et al. September 27, 1 | 1988-09-27 |
Branch prediction mechanism in which a branch history table is updated using an operand sensitive branch table
Grant 4,763,245 - Emma , et al. August 9, 1 | 1988-08-09 |
Pageable branch history table
Grant 4,679,141 - Pomerene , et al. July 7, 1 | 1987-07-07 |
Apparatus for addressing a larger number of instruction addressable central processor registers than can be identified by a program instruction
Grant 4,574,349 - Rechtschaffen March 4, 1 | 1986-03-04 |
Cache memory architecture with decoding
Grant 4,437,149 - Pomerene , et al. March 13, 1 | 1984-03-13 |
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