Rearick; Jeff

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rearick; Jeff.The latest application filed is for "generating test patterns for testing an integrated circuit".

Company Profile

0.15.11

Rearick; Jeff - Ft Collins CO
Rearick, Jeff - Court Ft Collins CO
Rearick; Jeff - Fort Collins CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Hierarchically-controlled automatic test pattern generation Grant 7,139,955 - Rohrbaugh , et al. November 21, 2	2006-11-21
Method and apparatus for deriving a bounded set of path delay test patterns covering all transition faults Grant 7,039,845 - Rearick , et al. May 2, 2	2006-05-02
System and method for evaluating an integrated circuit design Grant 6,944,837 - Rohrbaugh , et al. September 13, 2	2005-09-13
Partitioning integrated circuit hierarchy Grant 6,895,562 - Rohrbaugh , et al. May 17, 2	2005-05-17
Apparatus and method for generating a set of test vectors using nonrandom filling Grant 6,865,706 - Rohrbaugh , et al. March 8, 2	2005-03-08
Generating test patterns for testing an integrated circuit App 20040187060 - Rohrbaugh, John G. ; et al.	2004-09-23
Hierarchically-controlled automatic test pattern generation App 20040153928 - Rohrbaugh, John G. ; et al.	2004-08-05
Method and apparatus of boundary scan testing for AC-coupled differential data paths Grant 6,763,486 - Lai , et al. July 13, 2	2004-07-13
Systems and methods for testing tri-state bus drivers App 20040123194 - Rohrbaugh, John G. ; et al.	2004-06-24
System and method for evaluating an integrated circuit design App 20040123206 - Rohrbaugh, John G. ; et al.	2004-06-24
Systems and methods for testing tri-state bus drivers App 20040123195 - Rohrbaugh, John G. ; et al.	2004-06-24
Method and apparatus for testing current sinking/sourcing capability of a driver circuit Grant 6,737,858 - Rearick , et al. May 18, 2	2004-05-18
Systems and methods for facilitating testing of pad drivers of integrated circuits Grant 6,721,920 - Rearick , et al. April 13, 2	2004-04-13
Method for reducing stored patterns for IC test by embedding built-in-self-test circuitry for chip logic into a scan test access port Grant 6,715,105 - Rearick March 30, 2	2004-03-30
Method and apparatus for measuring the quality of delay test patterns Grant 6,708,139 - Rearick , et al. March 16, 2	2004-03-16
Systems and methods for testing integrated circuits Grant 6,707,313 - Rohrbaugh , et al. March 16, 2	2004-03-16
Partitioning integrated circuit hierarchy App 20040044972 - Rohrbaugh, John G. ; et al.	2004-03-04
SERDES cooperates with the boundary scan test technique Grant 6,653,957 - Patterson , et al. November 25, 2	2003-11-25
Method and apparatus for measuring the quality of delay test patterns App 20030204350 - Rearick, Jeff ; et al.	2003-10-30
Method and apparatus for deriving a bounded set of path delay test patterns covering all transition faults App 20030188246 - Rearick, Jeff ; et al.	2003-10-02
Method and apparatus for testing current sinking/sourcing capability of a driver circuit App 20030173989 - Rearick, Jeff ; et al.	2003-09-18
Systems and methods for facilitating testing of pad drivers of integrated circuits App 20020188901 - Rearick, Jeff ; et al.	2002-12-12
Method and apparatus of boundary scan testing for AC-coupled differential data paths App 20020170011 - Lai, Benny W. H. ; et al.	2002-11-14
Gate transition counter Grant 6,396,312 - Shepston , et al. May 28, 2	2002-05-28
Simulation-based method for estimating leakage currents in defect-free integrated circuits Grant 6,239,607 - Maxwell , et al. May 29, 2	2001-05-29
Highly compressible representation of test pattern data Grant 5,905,986 - Rohrbaugh , et al. May 18, 1	1999-05-18

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