loadpatents
Patent applications and USPTO patent grants for Realov; Simeon.The latest application filed is for "high performance fast mux-d scan flip-flop".
Patent | Date |
---|---|
Multibit vectored sequential with scan Grant 11,442,103 - Agarwal , et al. September 13, 2 | 2022-09-13 |
Low-power single-edge triggered flip-flop, and time borrowing internally stitched flip-flop Grant 11,398,814 - Hsu , et al. July 26, 2 | 2022-07-26 |
High Performance Fast Mux-d Scan Flip-flop App 20220224316 - Agarwal; Amit ;   et al. | 2022-07-14 |
High performance fast Mux-D scan flip-flop Grant 11,296,681 - Agarwal , et al. April 5, 2 | 2022-04-05 |
Low-power Single-edge Triggered Flip-flop, And Time Borrowing Internally Stitched Flip-flop App 20210281250 - Hsu; Steven ;   et al. | 2021-09-09 |
Multibit Vectored Sequential With Scan App 20210263100 - Agarwal; Amit ;   et al. | 2021-08-26 |
Double edge triggered Mux-D scan flip-flop Grant 11,054,470 - Agarwal , et al. July 6, 2 | 2021-07-06 |
Low Power Flip-flop With Reduced Parasitic Capacitance App 20210203323 - Hsu; Steven ;   et al. | 2021-07-01 |
High Performance Fast Mux-d Scan Flip-flop App 20210194469 - Agarwal; Amit ;   et al. | 2021-06-24 |
Double Edge Triggered Mux-d Scan Flip-flop App 20210194468 - Agarwal; Amit ;   et al. | 2021-06-24 |
Multibit vectored sequential with scan Grant 11,009,549 - Agarwal , et al. May 18, 2 | 2021-05-18 |
Vectored Flip-flop App 20210119616 - HSU; Steven K. ;   et al. | 2021-04-22 |
Vectored flip-flop Grant 10,862,462 - Hsu , et al. December 8, 2 | 2020-12-08 |
Multibit Vectored Sequential With Scan App 20200150179 - Agarwal; Amit ;   et al. | 2020-05-14 |
Vectored Flip-flop App 20200144995 - HSU; Steven K. ;   et al. | 2020-05-07 |
Vectored flip-flop Grant 10,498,314 - Hsu , et al. De | 2019-12-03 |
Low-power clock gate circuit Grant 10,491,217 - Hsu , et al. Nov | 2019-11-26 |
Multibit vectored sequential with scan Grant 10,473,718 - Agarwal , et al. Nov | 2019-11-12 |
Time borrowing flip-flop with clock gating scan multiplexer Grant 10,382,019 - Agarwal , et al. A | 2019-08-13 |
Multibit Vectored Sequential With Scan App 20190187208 - Agarwal; Amit ;   et al. | 2019-06-20 |
Low-power Clock Gate Circuit App 20190044511 - HSU; Steven ;   et al. | 2019-02-07 |
Shared keeper and footer flip-flop Grant 10,193,536 - Agarwal , et al. Ja | 2019-01-29 |
Integrated clock gate circuit with embedded NOR Grant 10,177,765 - Hsu , et al. J | 2019-01-08 |
Time Borrowing Flip-flop With Clock Gating Scan Multiplexer App 20180278243 - Agarwal; Amit ;   et al. | 2018-09-27 |
Time borrowing flip-flop with clock gating scan multiplexer Grant 9,985,612 - Agarwal , et al. May 29, 2 | 2018-05-29 |
Shared Keeper And Footer Flip-flop App 20180145663 - Agarwal; Amit ;   et al. | 2018-05-24 |
Integrated Clock Gate Circuit With Embedded Nor App 20180062658 - Hsu; Steven K. ;   et al. | 2018-03-01 |
Time Borrowing Flip-flop With Clock Gating Scan Multiplexer App 20180062625 - Agarwal; Amit ;   et al. | 2018-03-01 |
Shared keeper and footer flip-flop Grant 9,859,876 - Agarwal , et al. January 2, 2 | 2018-01-02 |
Vectored Flip-flop App 20170359054 - HSU; Steven K. ;   et al. | 2017-12-14 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.