| Patent | Date |
|---|
Logic for implementing a dual clock domain read access with predictable timing for bi-directional inputs/outputs
Grant 7,934,057 - Raza April 26, 2 | 2011-04-26 |
Device that provides the functionality of dual-ported memory using single-ported memory for multiple clock domains
Grant 7,738,496 - Raza June 15, 2 | 2010-06-15 |
Method and apparatus for aggregating Ethernet streams
Grant 7,382,805 - Raza , et al. June 3, 2 | 2008-06-03 |
Method and device for selecting one of multiple clock signals based on frequency differences of such clock signals
Grant 7,343,510 - Ross , et al. March 11, 2 | 2008-03-11 |
Method and architecture for synchronizing a path generator and/or extractor to a processor
Grant 7,334,147 - Raza February 19, 2 | 2008-02-19 |
System and method for staging concurrent accesses to a memory address location via a single port using a high speed sampling clock
Grant 7,184,359 - Bridgewater , et al. February 27, 2 | 2007-02-27 |
Logic for generating multicast/unicast address (es)
Grant 7,016,349 - Raza , et al. March 21, 2 | 2006-03-21 |
Architecture for implementing virtual multiqueue fifos
Grant 6,925,506 - Raza , et al. August 2, 2 | 2005-08-02 |
Method, architecture and circuitry for controlling pulse width in a phase and/or frequency detector
Grant 6,917,661 - Scott , et al. July 12, 2 | 2005-07-12 |
Logic for providing arbitration for synchronous dual-port memory
Grant 6,816,955 - Raza , et al. November 9, 2 | 2004-11-09 |
Configurable fast clock detection logic with programmable resolution
Grant 6,816,979 - Chen , et al. November 9, 2 | 2004-11-09 |
FIFO read interface protocol
Grant 6,810,098 - Paul , et al. October 26, 2 | 2004-10-26 |
Out-of-band look-ahead arbitration method and/or architecture
Grant 6,715,021 - Paul , et al. March 30, 2 | 2004-03-30 |
Overhead serial communication scheme
Grant 6,665,265 - Raza December 16, 2 | 2003-12-16 |
Circuit, system, and method for programmably setting an input to a prioritizer of a latch to avoid a non-desired output state of the latch
Grant 6,657,472 - Raza , et al. December 2, 2 | 2003-12-02 |
Architecture for multi-queue storage element
Grant 6,640,267 - Raza October 28, 2 | 2003-10-28 |
Method and apparatus for width and depth expansion in a multi-queue system
Grant 6,640,300 - Raza October 28, 2 | 2003-10-28 |
Logic for initializing the depth of the queue pointer memory
Grant 6,631,455 - Raza , et al. October 7, 2 | 2003-10-07 |
Circuit, method and/or architecture for improving the performance of a serial communication link
Grant 6,628,656 - Raza September 30, 2 | 2003-09-30 |
Fifo read interface protocol
Grant 6,629,226 - Paul , et al. September 30, 2 | 2003-09-30 |
Circuit, method and/or architecture for improving the performance of a serial communication link
Grant 6,625,177 - Raza September 23, 2 | 2003-09-23 |
Method and/or architecture for implementing queue expansion in multiqueue devices
Grant 6,625,711 - Raza , et al. September 23, 2 | 2003-09-23 |
Highly scalable architecture for implementing switch fabrics with quality of services
Grant 6,603,771 - Raza August 5, 2 | 2003-08-05 |
Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
Grant 6,243,664 - Nazarian , et al. June 5, 2 | 2001-06-05 |
Architecture for a dual segment dual speed repeater
Grant 6,195,360 - Raza , et al. February 27, 2 | 2001-02-27 |
Slew rate control circuit for an integrated circuit
Grant 5,986,489 - Raza , et al. November 16, 1 | 1999-11-16 |
Circuit for high speed serial programming of programmable logic devices
Grant 5,748,559 - Raza , et al. May 5, 1 | 1998-05-05 |
Methods for maximizing routability in a programmable interconnect matrix having less than full connectability
Grant 5,689,686 - Nazarian , et al. November 18, 1 | 1997-11-18 |
High speed programmable macrocell with combined path for storage and combinatorial modes
Grant 5,635,856 - Raza , et al. June 3, 1 | 1997-06-03 |
| 