Ray; Shishir

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ray; Shishir.The latest application filed is for "method for forming a shallow trench isolation structure using a nitride liner and a diffusionless anneal".

Company Profile

0.6.7

Ray; Shishir - Clifton Park NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method For Forming A Shallow Trench Isolation Structure Using A Nitride Liner And A Diffusionless Anneal App 20180040505 - Gaan; Sandeep ; et al.	2018-02-08
Devices comprising high-K dielectric layer and methods of forming same Grant 9,673,039 - Ray , et al. June 6, 2	2017-06-06
Integrated circuits and methods for their fabrication Grant 9,640,423 - Krishnan , et al. May 2, 2	2017-05-02
Semiconductor substrates and methods for processing semiconductor substrates Grant 9,570,291 - Ray , et al. February 14, 2	2017-02-14
Integrated Circuits And Methods For Their Fabrication App 20170033178 - Krishnan; Bharat ; et al.	2017-02-02
Fabricating transistors having resurfaced source/drain regions with stressed portions Grant 9,559,166 - Ray , et al. January 31, 2	2017-01-31
Semiconductor Substrates And Methods For Processing Semiconductor Substrates App 20170018426 - Ray; Shishir ; et al.	2017-01-19
Devices Comprising High-k Dielectric Layer And Methods Of Forming Same App 20160284540 - RAY; Shishir ; et al.	2016-09-29
Constrained nanosecond laser anneal of metal interconnect structures Grant 9,412,658 - Gluschenkov , et al. August 9, 2	2016-08-09
Fabricating Transistors Having Resurfaced Source/drain Regions With Stressed Portions App 20160225852 - RAY; Shishir ; et al.	2016-08-04
Constrained Nanosecond Laser Anneal Of Metal Interconnect Structures App 20160086849 - Gluschenkov; Oleg ; et al.	2016-03-24
Integrated Circuits With Stressed Semiconductor Substrates And Processes For Preparing Integrated Circuits Including The Stressed Semiconductor Substrates App 20150287824 - Ray; Shishir ; et al.	2015-10-08
Method of fabricating an interlayer structure of increased elasticity modulus Grant 9,076,645 - Ray , et al. July 7, 2	2015-07-07

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