Ravi; Ajay K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ravi; Ajay K..The latest application filed is for "integrated circuits with dual-edge clocking".

Company Profile

0.7.3

Ravi; Ajay K. - San Jose CA
Ravi; Ajay K - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuits with dual-edge clocking Grant 8,912,834 - Ravi , et al. December 16, 2	2014-12-16
Integrated Circuits With Dual-edge Clocking App 20130328606 - Ravi; Ajay K. ; et al.	2013-12-12
Integrated circuits with dual-edge clocking Grant 8,519,763 - Ravi , et al. August 27, 2	2013-08-27
Common clock path pessimism analysis for circuit designs using clock tree networks Grant 8,205,178 - Ravi June 19, 2	2012-06-19
Integrated Circuits With Dual-edge Clocking App 20110304371 - Ravi; Ajay K. ; et al.	2011-12-15
Common Clock Path Pessimism Analysis for Circuit Designs Using Clock Tree Networks App 20110239173 - Ravi; Ajay K.	2011-09-29
Determination of most critical timing paths in digital circuits Grant 8,028,260 - Ravi September 27, 2	2011-09-27
Common clock path pessimism analysis for circuit designs using clock tree networks Grant 7,926,019 - Ravi April 12, 2	2011-04-12
Methods to find worst-case setup and hold relationship for static timing analysis Grant 7,424,692 - Ravi September 9, 2	2008-09-09

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