Rausch; Werner

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rausch; Werner.The latest application filed is for "cmos diodes with dual gate conductors, and methods for forming the same".

Company Profile

0.19.11

Rausch; Werner - Stormville NY
Rausch; Werner - Oberursel DE
Rausch; Werner - Stierstadt/TS DT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
CMOS diodes with dual gate conductors, and methods for forming the same Grant 8,222,702 - Onsongo , et al. July 17, 2	2012-07-17
Structure and method for fabricating self-aligned metal contacts Grant 7,981,751 - Zhu , et al. July 19, 2	2011-07-19
Cmos Diodes With Dual Gate Conductors, And Methods For Forming The Same App 20100252881 - Onsongo; David M. ; et al.	2010-10-07
CMOS diodes with dual gate conductors, and methods for forming the same Grant 7,737,500 - Onsongo , et al. June 15, 2	2010-06-15
CMOS well structure and method of forming the same Grant 7,709,365 - Haensch , et al. May 4, 2	2010-05-04
Structure And Method For Fabricating Self-aligned Metal Contacts App 20100035400 - Zhu; Huilong ; et al.	2010-02-11
Structure and method for fabricating self-aligned metal contacts Grant 7,615,831 - Zhu , et al. November 10, 2	2009-11-10
Structure And Method For Fabricating Self-aligned Metal Contacts App 20090108378 - Zhu; Huilong ; et al.	2009-04-30
CMOS circuits including a passive element having a low end resistance Grant 7,491,598 - Sheraw , et al. February 17, 2	2009-02-17
Method of manufacturing a body-contacted finfet Grant 7,485,520 - Zhu , et al. February 3, 2	2009-02-03
Body-contacted Finfet App 20090008705 - Zhu; Huilong ; et al.	2009-01-08
Cmos Circuits Including A Passive Element Having A Low End Resistance App 20080096342 - Sheraw; Christopher D. ; et al.	2008-04-24
CMOS circuits including a passive element having a low end resistance Grant 7,361,959 - Sheraw , et al. April 22, 2	2008-04-22
Improved Cmos Diodes With Dual Gate Conductors, And Methods For Forming The Same App 20070252212 - Onsongo; David M. ; et al.	2007-11-01
Cmos Circuits Incorporating Passive Elements Of Low Contact Resistance, And Methods Of Forming Same App 20070120195 - Sheraw; Christopher D. ; et al.	2007-05-31
Cmos Well Structure And Method Of Forming The Same App 20070045749 - Haensch; Wilfried ; et al.	2007-03-01
SOI MOSFETS exhibiting reduced floating-body effects Grant 7,163,866 - Assaderaghi , et al. January 16, 2	2007-01-16
CMOS well structure and method of forming the same Grant 7,132,323 - Haensch , et al. November 7, 2	2006-11-07
CMOS well structure and method of forming the same App 20050106800 - Haensch, Wilfried ; et al.	2005-05-19
SOI MOSFETS exhibiting reduced floating-body effects App 20040142515 - Assaderaghi, Fariborz ; et al.	2004-07-22
T-RAM array having a planar cell structure and method for fabricating the same Grant 6,713,791 - Hsu , et al. March 30, 2	2004-03-30
SOI MOSFETS exhibiting reduced floating-body effects Grant 6,686,629 - Assaderaghi , et al. February 3, 2	2004-02-03
Method of integrating substrate contact on SOI wafers with STI process Grant 6,521,947 - Ajmera , et al. February 18, 2	2003-02-18
T-RAM array having a planar cell structure and method for fabricating the same App 20020100918 - Hsu, Louis L. ; et al.	2002-08-01
Process of making buried capacitor for silicon-on-insulator structure Grant 6,337,253 - Davari , et al. January 8, 2	2002-01-08
CMOS device structures and method of making same Grant 6,303,450 - Park , et al. October 16, 2	2001-10-16
Buried capacitor for silicon-on-insulator structure Grant 6,188,122 - Davari , et al. February 13, 2	2001-02-13
Process for a passivating postrinsing of conversion layers Grant 5,294,266 - Hauffe , et al. March 15, 1	1994-03-15
Composition and process for the phosphatizing of metals Grant 4,389,260 - Hauffe , et al. June 21, 1	1983-06-21
Metal-treating Process Grant 3,632,447 - Albrecht , et al. January 4, 1	1972-01-04

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