Rathore; Hazara S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rathore; Hazara S..The latest application filed is for "method and structure for determining thermal cycle reliability".

Company Profile

0.19.12

Rathore; Hazara S. - Stormville NY
Rathore; Hazara S. - Dutchess County NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method and structure for determining thermal cycle reliability Grant 9,443,776 - Filippi , et al. September 13, 2	2016-09-13
Method And Structure For Determining Thermal Cycle Reliability App 20150262899 - FILIPPI; RONALD G. ; et al.	2015-09-17
Method for prediction of premature dielectric breakdown in a semiconductor Grant 8,053,257 - Chanda , et al. November 8, 2	2011-11-08
Structure for modeling stress-induced degradation of conductive interconnects Grant 7,692,439 - Chanda , et al. April 6, 2	2010-04-06
Structure for monitoring stress-induced degradation of conductive interconnects Grant 7,639,032 - Chanda , et al. December 29, 2	2009-12-29
Dual damascene multi-level metallization Grant 7,470,613 - Agarwala , et al. December 30, 2	2008-12-30
Structure for modeling stress-induced degradation of conductive interconnects App 20080231312 - Chanda; Kaushik ; et al.	2008-09-25
Method For Prediction Of Premature Dielectric Breakdown In A Semiconductor App 20080174334 - Chanda; Kaushik ; et al.	2008-07-24
Structure and method for monitoring stress-induced degradation of conductive interconnects Grant 7,397,260 - Chanda , et al. July 8, 2	2008-07-08
Method for monitoring stress-induced degradation of conductive interconnects App 20080107149 - Chanda; Kaushik ; et al.	2008-05-08
Dual-damascene metallization interconnection Grant 7,224,063 - Agarwala , et al. May 29, 2	2007-05-29
Structure And Method For Monitoring Stress-induced Degradation Of Conductive Interconnects App 20070115018 - Chanda; Kaushik ; et al.	2007-05-24
Dual Damascene Multi-level Metallization App 20070111510 - Agarwala; Birendra N. ; et al.	2007-05-17
Method For Prediction Of Premature Dielectric Breakdown In A Semiconductor App 20060281338 - Chanda; Kaushik ; et al.	2006-12-14
Via barrier layers continuous with metal line barrier layers at notched or dielectric mesa portions in metal lines Grant 7,138,714 - Nguyen , et al. November 21, 2	2006-11-21
Reliability And Functionality Improvements On Copper Interconnects With Wide Metal Line Below The Via App 20060180930 - Nguyen; Du B. ; et al.	2006-08-17
Stacked via-stud with improved reliability in copper metallurgy App 20060014376 - Agarwala; Birendra N. ; et al.	2006-01-19
Stacked via-stud with improved reliability in copper metallurgy Grant 6,972,209 - Agarwala , et al. December 6, 2	2005-12-06
Structure And Method For Eliminating Time Dependent Dielectric Breakdown Failure Of Low-k Material App 20040256729 - Agarwala, Birendra N. ; et al.	2004-12-23
Structure and method for eliminating time dependent dielectric breakdown failure of low-k material Grant 6,825,561 - Agarwala , et al. November 30, 2	2004-11-30
Stacked via-stud with improved reliability in copper metallurgy App 20040101663 - Agarwala, Birendra N. ; et al.	2004-05-27
Dual damascene multi-level metallization App 20020182855 - Agarwala, Birendra N. ; et al.	2002-12-05
Copper interconnections with enhanced electromigration resistance and reduced defect sensitivity and method of forming same Grant 6,348,731 - Ashley , et al. February 19, 2	2002-02-19
Self-aligned composite insulator with sub-half-micron multilevel high density electrical interconnections and process thereof Grant 6,294,835 - Dalal , et al. September 25, 2	2001-09-25
Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity Grant 6,287,954 - Ashley , et al. September 11, 2	2001-09-11
Method of forming copper interconnections with enhanced electromigration resistance and reduced defect sensitivity Grant 6,130,161 - Ashley , et al. October 10, 2	2000-10-10
Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity Grant 6,069,068 - Rathore , et al. May 30, 2	2000-05-30
Method of producing planar metal-to-metal capacitor for use in integrated circuits Grant 6,069,051 - Nguyen , et al. May 30, 2	2000-05-30
Method for providing electrically fusible links in copper interconnection Grant 6,033,939 - Agarwala , et al. March 7, 2	2000-03-07
Sub-half-micron multi-level interconnection structure and process thereof Grant 5,981,374 - Dalal , et al. November 9, 1	1999-11-09
Method for producing interlevel stud vias Grant 5,252,516 - Nguyen , et al. October 12, 1	1993-10-12

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