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Patent applications and USPTO patent grants for Rathbun; Irwin D..The latest application filed is for "dmos device with sealed channel processing".
Patent | Date |
---|---|
LOCOS self-aligned twin well with a co-planar silicon surface Grant 7,642,181 - Miller, Jr. , et al. January 5, 2 | 2010-01-05 |
Dmos Device With Sealed Channel Processing App 20080290426 - Miller; Gayle W. ;   et al. | 2008-11-27 |
DMOS device with sealed channel processing Grant 7,407,851 - Miller , et al. August 5, 2 | 2008-08-05 |
DMOS device with sealed channel processing App 20070221965 - Miller; Gayle W. ;   et al. | 2007-09-27 |
Locos self-aligned twin well with a co-planar silicon surface App 20070178677 - Miller; Gayle W. JR. ;   et al. | 2007-08-02 |
Protective envelope for a chip card App 20060124747 - Rathbun; Irwin D. ;   et al. | 2006-06-15 |
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