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Patent applications and USPTO patent grants for Rastegar; Bahador.The latest application filed is for "memory cache with automatic alliased entry invalidation and method of operation".
Patent | Date |
---|---|
Memory cache with automatic alliased entry invalidation and method of operation Grant 5,550,995 - Barrera , et al. August 27, 1 | 1996-08-27 |
Memory cache with interlaced data and method of operation Grant 5,499,204 - Barrera , et al. March 12, 1 | 1996-03-12 |
Control circuit for dual port memory Grant 5,428,632 - Rastegar June 27, 1 | 1995-06-27 |
Output driver circuit with body bias control for multiple power supply operation Grant 5,422,591 - Rastegar , et al. June 6, 1 | 1995-06-06 |
Cache tag parity detect circuit Grant 5,339,322 - Rastegar August 16, 1 | 1994-08-16 |
Integrated circuit memory device having flash clear Grant 5,311,477 - Rastegar May 10, 1 | 1994-05-10 |
Integrated circuit dual-port memory device having reduced capacitance Grant 5,287,322 - Rastegar February 15, 1 | 1994-02-15 |
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