Rasouli; Seid Hadi
Patent Applications and Registrations
Patent applications and USPTO patent grants for Rasouli; Seid Hadi.The latest application filed is for "layout construction for addressing electromigration".
- Rasouli; Seid Hadi - San Diego CA
| Patent | Date |
|---|---|
| Layout construction for addressing electromigration Grant 11,437,375 - Rasouli , et al. September 6, 2 | 2022-09-06 |
| Layout Construction For Addressing Electromigration App 20200168604 - RASOULI; Seid Hadi ; et al. | 2020-05-28 |
| Layout Construction For Addressing Electromigration App 20200152630 - RASOULI; Seid Hadi ; et al. | 2020-05-14 |
| Layout construction for addressing electromigration Grant 10,600,785 - Rasouli , et al. | 2020-03-24 |
| Layout construction for addressing electromigration Grant 10,580,774 - Rasouli , et al. | 2020-03-03 |
| Layout Construction For Addressing Electromigration App 20180342515 - RASOULI; Seid Hadi ; et al. | 2018-11-29 |
| Layout construction for addressing electromigration Grant 10,074,609 - Rasouli , et al. September 11, 2 | 2018-09-11 |
| Layout Construction For Addressing Electromigration App 20180211957 - RASOULI; Seid Hadi ; et al. | 2018-07-26 |
| Clock Gating Cell For Low Setup Time For High Frequency Designs App 20180167058 - Rasouli; Seid Hadi ; et al. | 2018-06-14 |
| Pulse-stretcher Clock Generator Circuit For High Speed Memory Subsystems App 20180158506 - KUMAR; Dorav ; et al. | 2018-06-07 |
| Pulse-stretcher clock generator circuit for high speed memory subsystems Grant 9,990,984 - Kumar , et al. June 5, 2 | 2018-06-05 |
| Semi-data gated flop with low clock power/low internal power with minimal area overhead Grant 9,979,381 - Rasouli , et al. May 22, 2 | 2018-05-22 |
| Layout construction for addressing electromigration Grant 9,972,624 - Rasouli , et al. May 15, 2 | 2018-05-15 |
| Semi-data Gated Flop With Low Clock Power/low Internal Power With Minimal Area Overhead App 20180123568 - Rasouli; Seid Hadi ; et al. | 2018-05-03 |
| Standard cell architecture for reduced parasitic resistance and improved datapath speed Grant 9,859,891 - Kumar , et al. January 2, 2 | 2018-01-02 |
| Standard Cell Architecture For Reduced Parasitic Resistance And Improved Datapath Speed App 20170373689 - KUMAR; Dorav ; et al. | 2017-12-28 |
| Layout construction for addressing electromigration Grant 9,786,663 - Rasouli , et al. October 10, 2 | 2017-10-10 |
| Low-area Low Clock-power Flip-flop App 20170257080 - RASOULI; Seid Hadi ; et al. | 2017-09-07 |
| Low-area low clock-power flip-flop Grant 9,755,618 - Rasouli , et al. September 5, 2 | 2017-09-05 |
| Layout Construction For Addressing Electromigration App 20170221826 - RASOULI; Seid Hadi ; et al. | 2017-08-03 |
| Flip-flop with reduced retention voltage Grant 9,673,786 - Rasouli , et al. June 6, 2 | 2017-06-06 |
| Clock-gating cell with low area, low power, and low setup time Grant 9,577,635 - Rasouli , et al. February 21, 2 | 2017-02-21 |
| Clock-gating Cell With Low Area, Low Power, And Low Setup Time App 20160211846 - RASOULI; Seid Hadi ; et al. | 2016-07-21 |
| High performance standard cell with continuous oxide definition and characterized leakage current Grant 9,318,476 - Chen , et al. April 19, 2 | 2016-04-19 |
| High Performance Standard Cell App 20150249076 - CHEN; XIANGDONG ; et al. | 2015-09-03 |
| High frequency synchronizer Grant 9,020,084 - Rasouli , et al. April 28, 2 | 2015-04-28 |
| Layout Construction For Addressing Electromigration App 20150054567 - RASOULI; Seid Hadi ; et al. | 2015-02-26 |
| Layout Construction For Addressing Electromigration App 20150054568 - RASOULI; Seid Hadi ; et al. | 2015-02-26 |
| Flip-flop With Reduced Retention Voltage App 20140306735 - Rasouli; Seid Hadi ; et al. | 2014-10-16 |
| Clock-gated Synchronizer App 20140225655 - Rasouli; Seid Hadi ; et al. | 2014-08-14 |
| High Frequency Synchronizer App 20140211893 - Rasouli; Seid Hadi ; et al. | 2014-07-31 |
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