Rashed; Mahbub

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rashed; Mahbub.The latest application filed is for "low-leakage sense circuit, memory circuit incorporating the low-leakage sense circuit, and method".

Company Profile

15.68.68

Rashed; Mahbub - Santa Clara CA
Rashed; Mahbub - Cupertino CA
Rashed; Mahbub - Sunnyvale CA
Rashed; Mahbub - Malta NY
- Santa Clara CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device with transistor local interconnects Grant 11,444,031 - Rashed , et al. September 13, 2	2022-09-13
Low-leakage Sense Circuit, Memory Circuit Incorporating The Low-leakage Sense Circuit, And Method App 20220215872 - Raj; Vivek ; et al.	2022-07-07
Single-rail memory circuit with row-specific voltage supply lines and boost circuits Grant 11,322,200 - Raj , et al. May 3, 2	2022-05-03
Low clock load dynamic dual output latch circuit Grant 11,218,137 - Saha , et al. January 4, 2	2022-01-04
Low Clock Load Dynamic Dual Output Latch Circuit App 20210320650 - SAHA; Uttam ; et al.	2021-10-14
Dynamic single input-dual output latch Grant 11,050,414 - Saha , et al. June 29, 2	2021-06-29
Semiconductor Device With Transistor Local Interconnects App 20210013150 - Rashed; Mahbub ; et al.	2021-01-14
Semiconductor device with transistor local interconnects Grant 10,833,018 - Rashed , et al. November 10, 2	2020-11-10
Electrostatic discharge protection device Grant 10,819,110 - Kumar , et al. October 27, 2	2020-10-27
Positive and negative full-range back-bias generator circuit structure Grant 10,678,287 - Siddiqi , et al.	2020-06-09
Structure and method for flexible power staple insertion Grant 10,658,294 - Kim , et al.	2020-05-19
Positive And Negative Full-range Back-bias Generator Circuit Structure App 20200117226 - Siddiqi; Arif A. ; et al.	2020-04-16
Structure And Method For Flexible Power Staple Insertion App 20190333853 - Kim; Juhan ; et al.	2019-10-31
Semiconductor Device With Transistor Local Interconnects App 20190326219 - Rashed; Mahbub ; et al.	2019-10-24
Electrostatic Discharge Protection Device App 20190267801 - KUMAR; Anil ; et al.	2019-08-29
Structure and method for flexible power staple insertion Grant 10,366,954 - Kim , et al. July 30, 2	2019-07-30
Context aware processing to resolve strong spacing effects due to strain relaxation in standard cell library Grant 10,360,334 - Jain , et al.	2019-07-23
FDSOI semiconductor device with contact enhancement layer and method of manufacturing Grant 10,347,543 - Baars , et al. July 9, 2	2019-07-09
Method, apparatus, and system for improved memory cell design having unidirectional layout using self-aligned double patterning Grant 10,340,288 - Kim , et al.	2019-07-02
Calibration devices for I/O driver circuits having switches biased differently for different temperatures Grant 10,333,497 - Kumar , et al.	2019-06-25
On-chip voltage generator for back-biasing field effect transistors in a circuit block Grant 10,303,196 - Jain , et al.	2019-05-28
Fdsoi Semiconductor Device With Contact Enhancement Layer And Method Of Manufacturing App 20190148245 - Baars; Peter ; et al.	2019-05-16
Circuit design having aligned power staples Grant 10,242,946 - Lin , et al.	2019-03-26
Special construct for continuous non-uniform active region FinFET standard cells Grant 10,199,378 - Jain , et al. Fe	2019-02-05
Power Rail And Mol Constructs For Fdsoi App 20180315708 - MITTAL; Anurag ; et al.	2018-11-01
Method, apparatus and system for forming recolorable standard cells with triple patterned metal layer structures Grant 10,108,771 - Kim , et al. October 23, 2	2018-10-23
Antenna diode circuit for manufacturing of semiconductor devices Grant 10,096,595 - Kim , et al. October 9, 2	2018-10-09
Context Aware Processing To Resolve Strong Spacing Effects Due To Strain Relaxation In Standard Cell Library App 20180225406 - Jain; Navneet ; et al.	2018-08-09
Circuit Design Having Aligned Power Staples App 20180218981 - Lin; Irene Y. L. ; et al.	2018-08-02
Special Construct For Continuous Non-uniform Active Region Finfet Standard Cells App 20180122804 - JAIN; Navneet ; et al.	2018-05-03
Special construct for continuous non-uniform active region FinFET standard cells Grant 9,893,063 - Jain , et al. February 13, 2	2018-02-13
Method, Apparatus, And System For Improved Memory Cell Design Having Unidirectional Layout Using Self-aligned Double Patterning App 20180040631 - Kim; Juhan ; et al.	2018-02-08
Method, apparatus and system for using hybrid library track design for SOI technology Grant 9,842,184 - Mittal , et al. December 12, 2	2017-12-12
Method, Apparatus And System For Forming Recolorable Standard Cells With Triple Patterned Metal Layer Structures App 20170316140 - Kim; Juhan ; et al.	2017-11-02
Special Construct For Continuous Non-uniform Active Region Finfet Standard Cells App 20170141109 - JAIN; Navneet ; et al.	2017-05-18
Antenna Diode Circuit For Manufacturing Of Semiconductor Devices App 20170125403 - Kim; Juhan ; et al.	2017-05-04
Special construct for continuous non-uniform RX FinFET standard cells Grant 9,634,003 - Jain , et al. April 25, 2	2017-04-25
Method, Apparatus And System For Using Hybrid Library Track Design For Soi Technology App 20170076031 - Mittal; Anurag ; et al.	2017-03-16
Method, Apparatus And System For Using Tunable Timing Circuits For Fdsoi Technology App 20170063357 - Mittal; Anurag ; et al.	2017-03-02
Wide pin for improved circuit routing Grant 9,536,035 - Yuan , et al. January 3, 2	2017-01-03
Memory bit cell for reduced layout area Grant 9,530,780 - Kim , et al. December 27, 2	2016-12-27
Method and apparatus for assisted metal routing Grant 9,519,745 - Yuan , et al. December 13, 2	2016-12-13
Methods, Apparatus And System For Fabricating Finfet Devices Using Continuous Active Area Design App 20160336183 - Yuan; Lei ; et al.	2016-11-17
Memory Bit Cell For Reduced Layout Area App 20160322367 - KIM; Juhan ; et al.	2016-11-03
Semiconductor Device With Transistor Local Interconnects App 20160268204 - Rashed; Mahbub ; et al.	2016-09-15
Special Construct For Continuous Non-uniform Rx Finfet Standard Cells App 20160225763 - JAIN; Navneet ; et al.	2016-08-04
Memory bit cell for reduced layout area Grant 9,391,080 - Kim , et al. July 12, 2	2016-07-12
Semiconductor device with transistor local interconnects Grant 9,355,910 - Rashed , et al. May 31, 2	2016-05-31
Special constructs for continuous non-uniform active region FinFET standard cells Grant 9,337,099 - Jain , et al. May 10, 2	2016-05-10
Method And Apparatus For Assisted Metal Routing App 20160117432 - YUAN; Lei ; et al.	2016-04-28
Method and apparatus for modified cell architecture and the resulting device Grant 9,292,647 - Yuan , et al. March 22, 2	2016-03-22
Methods of using a trench salicide routing layer Grant 9,196,548 - Rashed , et al. November 24, 2	2015-11-24
Wide Pin For Improved Circuit Routing App 20150331988 - Yuan; Lei ; et al.	2015-11-19
Forming Gate Tie Between Abutting Cells And Resulting Device App 20150311122 - RASHED; Mahbub ; et al.	2015-10-29
Cross-coupling-based design using diffusion contact structures Grant 9,159,724 - Wang , et al. October 13, 2	2015-10-13
Forming modified cell architecture for finFET technology and resulting device Grant 9,147,028 - Rashed , et al. September 29, 2	2015-09-29
Middle-of-the-line constructs using diffusion contact structures Grant 9,142,513 - Rashed , et al. September 22, 2	2015-09-22
Wide pin for improved circuit routing Grant 9,122,830 - Yuan , et al. September 1, 2	2015-09-01
Bit cell with double patterned metal layer structures Grant 9,105,643 - Kim , et al. August 11, 2	2015-08-11
Method And Apparatus For Modified Cell Architecture And The Resulting Device App 20150213184 - YUAN; Lei ; et al.	2015-07-30
Middle-of-the-line Constructs Using Diffusion Contact Structures App 20150187702 - RASHED; Mahbub ; et al.	2015-07-02
Standard cell connection for circuit routing Grant 9,035,679 - Yuan , et al. May 19, 2	2015-05-19
Power rail layout for dense standard cell library Grant 9,026,977 - Tarabbia , et al. May 5, 2	2015-05-05
Densely Packed Standard Cells For Integrated Circuit Products, And Methods Of Making Same App 20150108583 - Rashed; Mahbub ; et al.	2015-04-23
Middle-of-the-line constructs using diffusion contact structures Grant 9,006,100 - Rashed , et al. April 14, 2	2015-04-14
Cross-coupling based design using diffusion contact structures Grant 8,987,128 - Rashed , et al. March 24, 2	2015-03-24
Densely packed standard cells for integrated circuit products, and methods of making same Grant 8,975,712 - Rashed , et al. March 10, 2	2015-03-10
Integrating optimal planar and three-dimensional semiconductor design layouts Grant 8,966,423 - Jain , et al. February 24, 2	2015-02-24
Power Rail Layout For Dense Standard Cell Library App 20150052494 - TARABBIA; Marc ; et al.	2015-02-19
FinFET device and methods of fabrication Grant 8,916,441 - Rashed , et al. December 23, 2	2014-12-23
Wide Pin For Improved Circuit Routing App 20140353842 - Yuan; Lei ; et al.	2014-12-04
Parameterized cell for planar and finFET technology design Grant 8,904,324 - Jain , et al. December 2, 2	2014-12-02
Forming Modified Cell Architecture For Finfet Technology And Resulting Device App 20140346662 - RASHED; Mahbub ; et al.	2014-11-27
Densely Packed Standard Cells For Integrated Circuit Products, And Methods Of Making Same App 20140339647 - Rashed; Mahbub ; et al.	2014-11-20
Finfet Device And Method Of Fabrication App 20140339610 - Rashed; Mahbub ; et al.	2014-11-20
Bit Cell With Double Patterened Metal Layer Structures App 20140332967 - KIM; Juhan ; et al.	2014-11-13
Methods For Improving Double Patterning Route Efficiency App 20140327146 - Deng; Yunfei ; et al.	2014-11-06
Standard Cell Connection For Circuit Routing App 20140327153 - Yuan; Lei ; et al.	2014-11-06
Methods for improving double patterning route efficiency Grant 8,881,083 - Deng , et al. November 4, 2	2014-11-04
Software and method for via spacing in a semiconductor device Grant 8,859,416 - Doman , et al. October 14, 2	2014-10-14
Parameterized Cell For Planar And Finfet Technology Design App 20140282323 - Jain; Navneet ; et al.	2014-09-18
Integrating Optimal Planar And Three-dimensional Semiconductor Design Layouts App 20140258960 - Jain; Navneet ; et al.	2014-09-11
Bit cell with double patterned metal layer structures Grant 8,823,178 - Kim , et al. September 2, 2	2014-09-02
Variable power rail design Grant 8,789,000 - Rashed , et al. July 22, 2	2014-07-22
Methods Of Using A Trench Salicide Routing Layer App 20140183638 - RASHED; Mahbub ; et al.	2014-07-03
Layout designs with via routing structures Grant 8,741,763 - Ma , et al. June 3, 2	2014-06-03
Integrated circuits and methods for fabricating integrated circuits using double patterning processes Grant 8,735,050 - Yuan , et al. May 27, 2	2014-05-27
Cross-coupling-based Design Using Diffusion Contact Structures App 20140131816 - WANG; Yan ; et al.	2014-05-15
Double Patterning Compatible Colorless M1 Route App 20140097892 - Yuan; Lei ; et al.	2014-04-10
Providing timing-closed FinFET designs from planar designs Grant 8,689,154 - Rashed , et al. April 1, 2	2014-04-01
Cross-coupling-based design using diffusion contact structures Grant 8,679,911 - Wang , et al. March 25, 2	2014-03-25
Bit Cell With Double Patterned Metal Layer Structures App 20140077380 - Kim; Juhan ; et al.	2014-03-20
Double patterning compatible colorless M1 route Grant 8,677,291 - Yuan , et al. March 18, 2	2014-03-18
Middle-of-the-line Constructs Using Diffusion Contact Structures App 20140042641 - Rashed; Mahbub ; et al.	2014-02-13
Integrated Circuits And Methods For Fabricating Integrated Circuits Using Double Patterning Processes App 20140035151 - Yuan; Lei ; et al.	2014-02-06
Cross-coupling Based Design Using Diffusion Contact Structures App 20140027918 - Rashed; Mahbub ; et al.	2014-01-30
Semiconductor Devices Formed On A Continuous Active Region With An Isolating Conductive Structure Positioned Between Such Semiconductor Devices, And Methods Of Making Same App 20140001563 - Rashed; Mahbub ; et al.	2014-01-02
Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same Grant 08618607 -	2013-12-31
Semiconductor devices formed on a continuous active region with an isolating conductive structure positioned between such semiconductor devices, and methods of making same Grant 8,618,607 - Rashed , et al. December 31, 2	2013-12-31
Semiconductor device having contact layer providing electrical connections Grant 8,598,633 - Tarabbia , et al. December 3, 2	2013-12-03
Semiconductor device with transistor local interconnects Grant 8,581,348 - Rashed , et al. November 12, 2	2013-11-12
Cross-coupling-based Design Using Diffusion Contact Structures App 20130292773 - WANG; Yan ; et al.	2013-11-07
Layout Designs With Via Routing Structures App 20130292772 - Ma; Yuansheng ; et al.	2013-11-07
Software And Method For Via Spacing In A Semiconductor Device App 20130280905 - Doman; David S. ; et al.	2013-10-24
Providing Timing-closed Finfet Designs From Planar Designs App 20130275935 - Rashed; Mahbub ; et al.	2013-10-17
Semiconductor Device App 20130181289 - Tarabbia; Marc ; et al.	2013-07-18
Semiconductor Device With Transistor Local Interconnects App 20130146986 - Rashed; Mahbub ; et al.	2013-06-13
Semiconductor Device With Transistor Local Interconnects App 20130146982 - Rashed; Mahbub ; et al.	2013-06-13

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