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name:-0.05051589012146
name:-0.040233135223389
name:-0.021214962005615
Rappoport; Lihu Patent Filings

Rappoport; Lihu

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rappoport; Lihu.The latest application filed is for "apparatuses and methods for a processor architecture".

Company Profile
22.42.56
  • Rappoport; Lihu - Haifa IL
  • Rappoport; Lihu - Kiryat Tivon IL
  • Rappoport, Lihu - Halfa IL
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Apparatuses And Methods For A Processor Architecture
App 20220237123 - Brandt; Jason W. ;   et al.
2022-07-28
Technology For Dynamically Tuning Processor Features
App 20220206925 - Chauhan; Adarsh ;   et al.
2022-06-30
Apparatuses and methods for a processor architecture
Grant 11,294,809 - Brandt , et al. April 5, 2
2022-04-05
Technology for dynamically tuning processor features
Grant 11,256,599 - Chauhan , et al. February 22, 2
2022-02-22
Code Prefetch Instruction
App 20210342134 - Yasin; Ahmad ;   et al.
2021-11-04
Accelerating memory fault resolution by performing fast re-fetching
Grant 11,150,979 - Sperber , et al. October 19, 2
2021-10-19
Instruction length decoder system and method
Grant 11,086,627 - Tell , et al. August 10, 2
2021-08-10
Dual Write Micro-op Queue
App 20210200538 - SALA; Franck ;   et al.
2021-07-01
Loop Exit Predictor
App 20210200550 - SIVTSOV; Alexey Yurievich ;   et al.
2021-07-01
Technology For Dynamically Tuning Processor Features
App 20210109839 - Chauhan; Adarsh ;   et al.
2021-04-15
Instruction Length Decoder System and Method
App 20210096867 - Tell; Nir ;   et al.
2021-04-01
System, apparatus and method for context-based override of history-based branch predictions
Grant 10,949,208 - Gupta , et al. March 16, 2
2021-03-16
Technology for dynamically tuning processor features
Grant 10,915,421 - Chauhan , et al. February 9, 2
2021-02-09
Detecting A Dynamic Control Flow Re-convergence Point For Conditional Branches In Hardware
App 20210019149 - CHAUHAN; ADARSH ;   et al.
2021-01-21
Automatic predication of hard-to-predict convergent branches
Grant 10,754,655 - Chauhan , et al. A
2020-08-25
Criticality based port scheduling
Grant 10,719,355 - Roy , et al.
2020-07-21
System, Apparatus And Method For Context-Based Override Of History-Based Branch Predictions
App 20200192670 - Gupta; Saurabh ;   et al.
2020-06-18
Multicore system for fusing instructions queued during a dynamically adjustable time window
Grant 10,649,783 - Ouziel , et al.
2020-05-12
Apparatuses And Methods For Speculative Execution Side Channel Mitigation
App 20200133679 - Brandt; Jason W. ;   et al.
2020-04-30
Defragmented and efficient micro-operation cache
Grant 10,579,535 - Rappoport , et al.
2020-03-03
Automatic Predication Of Hard-to-predict Convergent Branches
App 20200004542 - Chauhan; Adarsh ;   et al.
2020-01-02
Accelerating Memory Fault Resolution By Performing Fast Re-fetching
App 20190370108 - Sperber; Zeev ;   et al.
2019-12-05
Thread pause processors, methods, systems, and instructions
Grant 10,467,011 - Rappoport , et al. No
2019-11-05
Accelerating memory fault resolution by performing fast re-fetching
Grant 10,402,263 - Sperber , et al. Sep
2019-09-03
Criticality Based Port Scheduling
App 20190243684 - Roy; Pooja ;   et al.
2019-08-08
Stream Cache
App 20190213131 - Sabba; Ariel ;   et al.
2019-07-11
Defragmented And Efficient Micro-operation Cache
App 20190188142 - RAPPOPORT; Lihu ;   et al.
2019-06-20
Accelerating Memory Fault Resolution By Performing Fast Re-fetching
App 20190171515 - Sperber; Zeev ;   et al.
2019-06-06
Apparatuses And Methods For A Processor Architecture
App 20190012266 - Brandt; Jason W. ;   et al.
2019-01-10
Instruction and logic for register based hardware memory renaming
Grant 10,095,522 - Garifullin , et al. October 9, 2
2018-10-09
Apparatuses And Methods For A Processor Architecture
App 20180165199 - Brandt; Jason W. ;   et al.
2018-06-14
System and method for fusing instructions queued during a time window defined by a delay counter
Grant 9,690,591 - Ouziel , et al. June 27, 2
2017-06-27
Hybrid threading
Grant 9,678,807 - Gendler , et al. June 13, 2
2017-06-13
Apparatus and method for efficient memory renaming prediction using virtual registers
Grant 9,552,169 - Rappoport , et al. January 24, 2
2017-01-24
Efficient Instruction Fusion By Fusing Instructions That Fall Within A Counter-tracked Amount Of Cycles Apart
App 20170003965 - Ouziel; Ido ;   et al.
2017-01-05
Efficient Instruction Fusion By Fusing Instructions That Fall Within A Counter-tracked Amount Of Cycles Apart
App 20160378487 - Ouziel; Ido ;   et al.
2016-12-29
Apparatus And Method For Efficient Memory Renaming Prediction Using Virtual Registers
App 20160328172 - RAPPOPORT; LIHU ;   et al.
2016-11-10
Apparatus and method for implement a multi-level memory hierarchy
Grant 9,448,879 - Yigzaw , et al. September 20, 2
2016-09-20
Efficient Instruction Fusion By Fusing Instructions That Fall Within A Counter-tracked Amount Of Cycles Apart
App 20160246600 - Ouziel; Ido ;   et al.
2016-08-25
Instruction And Logic For Register Based Hardware Memory Renaming
App 20160179545 - Garifullin; Kamil ;   et al.
2016-06-23
Multi-level tracking of in-use state of cache lines
Grant 9,348,591 - Kim , et al. May 24, 2
2016-05-24
Thread Pause Processors, Methods, Systems, And Instructions
App 20160019063 - Rappoport; Lihu ;   et al.
2016-01-21
Hybrid Threading
App 20150169365 - Gendler; Alexander ;   et al.
2015-06-18
Protecting the integrity of binary translated code
Grant 9,027,009 - Raikin , et al. May 5, 2
2015-05-05
Optimizing performance of instructions based on sequence detection or information associated with the instructions
Grant 8,935,514 - Falik , et al. January 13, 2
2015-01-13
Apparatus And Method For Implement A Multi-level Memory Hierarchy
App 20140298140 - Yigzaw; Theodros ;   et al.
2014-10-02
Protecting The Integrity Of Binary Translated Code
App 20140245273 - Raikin; Shlomo ;   et al.
2014-08-28
Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor
Grant 8,782,374 - Rappoport , et al. July 15, 2
2014-07-15
System Of Improved Loop Detection And Execution
App 20140189331 - Lipshits; Maria ;   et al.
2014-07-03
Optional Branches
App 20140189330 - Zaks; Ayal ;   et al.
2014-07-03
Optimizing Performance Of Instructions Based On Sequence Detection Or Information Associated With The Instructions
App 20130346728 - Falik; Ohad ;   et al.
2013-12-26
Multi-level Tracking Of In-use State Of Cache Lines
App 20130275733 - Kim; Ilhyun ;   et al.
2013-10-17
Optimizing performance of instructions based on sequence detection or information associated with the instructions
Grant 8,543,796 - Falik , et al. September 24, 2
2013-09-24
Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
Grant 8,433,850 - Rappoport , et al. April 30, 2
2013-04-30
Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
Grant 8,127,085 - Rappoport , et al. February 28, 2
2012-02-28
Efficient method and apparatus for employing a micro-op cache in a processor
Grant 8,103,831 - Rappoport , et al. January 24, 2
2012-01-24
Trace indexing via trace end addresses
Grant 7,802,077 - Jourdan , et al. September 21, 2
2010-09-21
Instruction segment recording scheme
Grant 7,757,065 - Jourdan , et al. July 13, 2
2010-07-13
Method And Apparatus For Inclusion Of Tlb Entries In A Micro-op Cache Of A Processor
App 20100138610 - Rappoport; Lihu ;   et al.
2010-06-03
Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
App 20100138608 - Rappoport; Lihu ;   et al.
2010-06-03
Method And Apparatus For Pipeline Inclusion And Instruction Restarts In A Micro-op Cache Of A Processor
App 20100138611 - RAPPOPORT; LIHU ;   et al.
2010-06-03
Optimizing performance of instructions based on sequence detection or information associated with the instructions
App 20100115240 - Falik; Ohad ;   et al.
2010-05-06
Technique for promoting efficient instruction fusion
App 20100115248 - Ouziel; Ido ;   et al.
2010-05-06
Memory cache bank prediction
Grant 7,644,236 - Yoaz , et al. January 5, 2
2010-01-05
Efficient Method And Apparatus For Employing A Micro-op Cache In A Processor
App 20090249036 - Rappoport; Lihu ;   et al.
2009-10-01
Method and apparatus for predicting values in a processor having a plurality of prediction modes
Grant 7,428,627 - Jourdan , et al. September 23, 2
2008-09-23
Method and system for branch target prediction using path information
App 20050262332 - Rappoport, Lihu ;   et al.
2005-11-24
Memory cache bank prediction
App 20050132138 - Yoaz, Adi ;   et al.
2005-06-16
Memory cache bank prediction
Grant 6,880,063 - Yoaz , et al. April 12, 2
2005-04-12
Memory cache bank prediction
App 20040143705 - Yoaz, Adi ;   et al.
2004-07-22
Cache memory bank access prediction
Grant 6,694,421 - Yoaz , et al. February 17, 2
2004-02-17
Cache structure for storing variable length data
Grant 6,631,445 - Rappoport , et al. October 7, 2
2003-10-07
Controlling population size of confidence assignments
Grant 6,625,744 - Rappoport , et al. September 23, 2
2003-09-23
Method and system for branch target prediction using path information
Grant 6,601,161 - Rappoport , et al. July 29, 2
2003-07-29
Cache structure for storing variable length data
App 20030131183 - Rappoport, Lihu ;   et al.
2003-07-10
Memory Cache Bank Prediction
App 20030051099 - YOAZ, ADI ;   et al.
2003-03-13
Method And System For Branch Target Prediction Using Path Information
App 20030041230 - RAPPOPORT, LIHU ;   et al.
2003-02-27
Correlated address prediction
Grant 6,438,673 - Jourdan , et al. August 20, 2
2002-08-20
Multi-mode non-binary predictor
App 20020087850 - Jourdan, Stephan J. ;   et al.
2002-07-04

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