Raorane; Digvijay A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Raorane; Digvijay A..The latest application filed is for "control of warpage using abf gc cavity for embedded die package".

Company Profile

13.20.31

Raorane; Digvijay A. - Chandler AZ
Raorane; Digvijay A. - Berkeley CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor package having passive support wafer Grant 11,417,630 - Mallik , et al. August 16, 2	2022-08-16
Control Of Warpage Using Abf Gc Cavity For Embedded Die Package App 20220230972 - RAORANE; Digvijay A. ; et al.	2022-07-21
Control of warpage using ABF GC cavity for embedded die package Grant 11,322,457 - Raorane , et al. May 3, 2	2022-05-03
Landing Pad Apparatus For Through-silicon-vias App 20210287975 - Raorane; Digvijay A.	2021-09-16
Embedded Bridge With Through-silicon Vias App 20210272881 - VAIDYA; Aditya S. ; et al.	2021-09-02
Embedded bridge with through-silicon Vias Grant 11,049,798 - Vaidya , et al. June 29, 2	2021-06-29
Barrier Materials Between Bumps And Pads App 20210057348 - HWANG; Ehren ; et al.	2021-02-25
Control Of Warpage Using Abf Gc Cavity For Embedded Die Package App 20200251426 - Kind Code	2020-08-06
Enclosure For An Electronic Component App 20200098655 - Nair; Vijay K. ; et al.	2020-03-26
Electronic Package Assembly With Stiffener App 20200083180 - MALLIK; Debendra ; et al.	2020-03-12
Electromagnetic Interference Shielding For Semiconductor Packages Using Bond Wires App 20200075501 - RAORANE; Digvijay A. ; et al.	2020-03-05
Embedded Bridge With Through-silicon Vias App 20190326198 - Vaidya; Aditya S. ; et al.	2019-10-24
Stacking Multiple Dies Having Dissimilar Interconnect Structure Layout And Pitch App 20190311983 - Raorane; Digvijay A. ; et al.	2019-10-10
Tamper resistant lock assembly having physical unclonable functions Grant 10,421,432 - Moore , et al. Sept	2019-09-24
Semiconductor Package Having Passive Support Wafer App 20190287942 - MALLIK; Debendra ; et al.	2019-09-19
Recessed Semiconductor Die In A Die Stack To Accomodate A Component App 20190287956 - Raorane; Digvijay A. ; et al.	2019-09-19
Electronic device package Grant 10,403,578 - Raorane , et al. Sep	2019-09-03
Embedded bridge with through-silicon vias Grant 10,373,893 - Vaidya , et al.	2019-08-06
Electronic package assembly with compact die placement Grant 10,373,888 - Li , et al.	2019-08-06
Method of forming an interference shield on a substrate Grant 10,375,832 - Raorane , et al.	2019-08-06
Bridge Hub Tiling Architecture App 20190206798 - COLLINS; ANDREW P. ; et al.	2019-07-04
Electronic Device Package App 20190103361 - Raorane; Digvijay A. ; et al.	2019-04-04
Die sidewall interconnects for 3D chip assemblies Grant 10,199,354 - Modi , et al. Fe	2019-02-05
Embedded Bridge With Through-silicon Vias App 20190006264 - Vaidya; Aditya S. ; et al.	2019-01-03
Tamper Resistant Lock Assembly Having Physical Unclonable Functions App 20180345904 - Moore; Victoria C. ; et al.	2018-12-06
Electronic Package Assembly With Compact Die Placement App 20180190560 - Li; Eric J. ; et al.	2018-07-05
Die Sidewall Interconnects For 3d Chip Assemblies App 20180174999 - MODI; Mitul ; et al.	2018-06-21
Multichip integration with through silicon via (TSV) die embedded in package Grant 9,716,084 - Raorane , et al. July 25, 2	2017-07-25
Bumpless build-up layer (BBUL) semiconductor package with ultra-thin dielectric layer Grant 9,520,350 - Teh , et al. December 13, 2	2016-12-13
Multichip Integration With Through Silicon Via (tsv) Die Embedded In Package App 20160322344 - Raorane; Digvijay A. ; et al.	2016-11-03
On Package Floating Metal/Stiffener Grounding to Mitigate RFI and SI Risks App 20160268213 - JIANG; Hongjin ; et al.	2016-09-15
Multichip integration with through silicon via (TSV) die embedded in package Grant 9,397,079 - Raorane , et al. July 19, 2	2016-07-19
Thin Film Based Electromagnetic Interference Shielding With Bbul/coreless Packages App 20160088738 - RAORANE; Digvijay A. ; et al.	2016-03-24
Thin film based electromagnetic interference shielding with BBUL/coreless packages Grant 9,232,686 - Raorane , et al. January 5, 2	2016-01-05
Thin Film Based Electromagnetic Interference Shielding With Bbul/coreless Packages App 20150282395 - RAORANE; Digvijay A. ; et al.	2015-10-01
Multichip Integration With Through Silicon Via (tsv) Die Embedded In Package App 20150171067 - Raorane; Digvijay A. ; et al.	2015-06-18
Method to increase I/O density and reduce layer counts in BBUL packages Grant 9,041,207 - Raorane , et al. May 26, 2	2015-05-26
Multichip integration with through silicon via (TSV) die embedded in package Grant 9,000,599 - Raorane , et al. April 7, 2	2015-04-07
Receptors useful for gas phase chemical sensing Grant 8,957,013 - Jaworski , et al. February 17, 2	2015-02-17
Method To Increase I/o Density And Reduce Layer Counts In Bbul Packages App 20150001730 - RAORANE; Digvijay A. ; et al.	2015-01-01
Multichip Integration With Through Silicon Via (tsv) Die Embedded In Package App 20140332975 - Raorane; Digvijay A. ; et al.	2014-11-13
Bumpless Build-up Layer (bbul) Semiconductor Package With Ultra-thin Dielectric Layer App 20140264830 - Teh; Weng Hong ; et al.	2014-09-18
Receptors Useful for Gas Phase Chemical Sensing App 20120108450 - Jaworski; Justyn W. ; et al.	2012-05-03

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