Rao; Vishwas M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rao; Vishwas M..The latest application filed is for "methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby".

Company Profile

0.16.16

Rao; Vishwas M. - San Jose CA
Rao; Vishwas M. - Breinigsville PA
Rao; Vishwas M. - Milpitas CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods For Designing Integrated Circuits Employing Voltage Scaling And Integrated Circuits Designed Thereby App 20140298277 - Parker; James C. ; et al.	2014-10-02
Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby Grant 8,806,408 - Parker , et al. August 12, 2	2014-08-12
Methods for designing integrated circuits employing pre-determined timing-realizable clock-insertion delays and integrated circuit design tools Grant 8,689,161 - Rao , et al. April 1, 2	2014-04-01
Hierarchical design flow generator Grant 8,683,407 - Rao , et al. March 25, 2	2014-03-25
Hierarchical Design Flow Generator App 20130339912 - Rao; Vishwas M. ; et al.	2013-12-19
Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow Grant 8,543,951 - Rao , et al. September 24, 2	2013-09-24
Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics Grant 8,539,423 - Jamann , et al. September 17, 2	2013-09-17
Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method Grant 8,539,419 - Rao , et al. September 17, 2	2013-09-17
Systematic Benchmarking System And Method For Standardized Data Creation, Analysis And Comparison Of Semiconductor Technology Node Characteristics App 20130104096 - Jamann; Joseph J. ; et al.	2013-04-25
Systematic, Normalized Metric For Analyzing And Comparing Optimization Techniques For Integrated Circuits Employing Voltage Scaling And Integrated Circuits Designed Thereby App 20130055175 - Jamann; Joseph J. ; et al.	2013-02-28
Novel Modeling Approach For Timing Closure In Hierarchical Designs Leveraging The Separation Of Horizontal And Vertical Aspects Of The Design Flow App 20130036393 - Rao; Vishwas M. ; et al.	2013-02-07
Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow Grant 8,341,573 - Rao , et al. December 25, 2	2012-12-25
Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics Grant 8,307,324 - Jamann , et al. November 6, 2	2012-11-06
Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed thereby Grant 8,281,266 - Jamann , et al. October 2, 2	2012-10-02
Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method Grant 8,239,805 - Rao , et al. August 7, 2	2012-08-07
Method For Designing Integrated Circuits Employing A Partitioned Hierarchical Design Flow And An Apparatus Employing The Method App 20120174048 - Rao; Vishwas M. ; et al.	2012-07-05
Novel Modeling Approach For Timing Closure In Hierarchical Designs Leveraging The Separation Of Horizontal And Vertical Aspects Of The Design Flow App 20120095746 - Rao; Vishwas M. ; et al.	2012-04-19
Methods for designing integrated circuits employing context-sensitive and progressive rules and an apparatus employing one of the methods Grant 8,127,264 - Parker , et al. February 28, 2	2012-02-28
Establishing benchmarks for analyzing benefits associated with voltage scaling, analyzing the benefits and an apparatus therefor Grant 8,122,422 - Rao , et al. February 21, 2	2012-02-21
Methods For Designing Integrated Circuits Employing Pre-determined Timing-realizable Clock-insertion Delays And Integrated Circuit Design Tools App 20120011484 - Rao; Vishwas M. ; et al.	2012-01-12
Systematic Benchmarking System And Method For Standardized Data Creation, Analysis And Comparison Of Semiconductor Technology Node Characteristics App 20110307852 - Jamann; Joseph J. ; et al.	2011-12-15
Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics Grant 8,024,694 - Jamann , et al. September 20, 2	2011-09-20
Method For Designing Integrated Circuits Employing A Partitioned Hierarchical Design Flow And An Apparatus Employing The Method App 20110022998 - Rao; Vishwas M. ; et al.	2011-01-27
Methods For Designing Integrated Circuits Employing Context-sensitive And Progressive Rules And An Apparatus Employing One Of The Methods App 20110022996 - Parker; James C. ; et al.	2011-01-27
Establishing Benchmarks For Analyzing Benefits Associated With Voltage Scaling, Analyzing The Benefits And An Apparatus Therefor App 20110023004 - Rao; Vishwas M. ; et al.	2011-01-27
Systematic, Normalized Metric For Analyzing And Comparing Optimization Techniques For Integrated Circuits Employing Voltage Scaling And Integrated Circuits Designed Thereby App 20100037188 - Jamann; Joseph J. ; et al.	2010-02-11
Methods For Designing Integrated Circuits Employing Voltage Scaling And Integrated Circuits Designed Thereby App 20100026378 - Parker; James C. ; et al.	2010-02-04
Systematic Benchmarking System And Method For Standardized Data Creation, Analysis And Comparison Of Semiconductor Technology Node Characteristics App 20090281772 - Jamann; Joseph J. ; et al.	2009-11-12

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