Rao; Vasant B.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rao; Vasant B..The latest application filed is for "cognitive system to iteratively expand a knowledge base".

Company Profile

3.10.11

Rao; Vasant B. - Fishkill NY
Rao; Vasant B. - Hopewell Junction NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-cycle signal identification for static timing analysis Grant 10,360,329 - Allen , et al.	2019-07-23
Incremental common path pessimism analysis Grant 10,325,059 - Huang , et al.	2019-06-18
Cognitive System To Iteratively Expand A Knowledge Base App 20190138916 - Allen; Robert J. ; et al.	2019-05-09
Incremental Common Path Pessimism Analysis App 20180046748 - Huang; Tsung-Wei ; et al.	2018-02-15
Incremental common path pessimism analysis Grant 9,836,572 - Huang , et al. December 5, 2	2017-12-05
Parallel multi-threaded common path pessimism removal in multiple paths Grant 9,785,737 - Hathaway , et al. October 10, 2	2017-10-10
Validating variation of timing constraint measurements Grant 9,760,665 - Gupta , et al. September 12, 2	2017-09-12
Validating variation of timing constraint measurements Grant 9,760,664 - Gupta , et al. September 12, 2	2017-09-12
Multi-cycle Signal Identification For Static Timing Analysis App 20170206294 - Allen; Robert J. ; et al.	2017-07-20
Incremental Common Path Pessimism Analysis App 20170147737 - Huang; Tsung-Wei ; et al.	2017-05-25
Parallel Multi-threaded Common Path Pessimism Removal In Multiple Paths App 20170140089 - Hathaway; David J. ; et al.	2017-05-18
Multi-cycle signal identification for static timing analysis Grant 9,613,171 - Allen , et al. April 4, 2	2017-04-04
Validating Variation of Timing Constraint Measurements App 20170011154 - GUPTA; SACHIN K. ; et al.	2017-01-12
Validating Variation of Timing Constraint Measurements App 20170011153 - GUPTA; SACHIN K. ; et al.	2017-01-12
Timing Analysis Of Circuits Using Sub-circuit Timing Models App 20160364519 - Allen; Robert J. ; et al.	2016-12-15
Timing analysis of circuits using sub-circuit timing models Grant 9,501,608 - Allen , et al. November 22, 2	2016-11-22
Pulse waveform timing in EinsTLT templates Grant 7,643,981 - Lee , et al. January 5, 2	2010-01-05
Pulse waveform timing in EinsTLT templates App 20060020443 - Lee; Sang Y. ; et al.	2006-01-26
Method for reducing RC parasitics in interconnect networks of an integrated circuit Grant 6,763,504 - Rao , et al. July 13, 2	2004-07-13
Method for reducing RC parasitics in interconnect networks of an integrated circuit App 20040049746 - Rao, Vasant B. ; et al.	2004-03-11
Circuit simulator system and method App 20030182639 - Lehner, Timothy S. ; et al.	2003-09-25

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