loadpatents
name:-0.051528930664062
name:-0.033569097518921
name:-0.0026581287384033
Rao; Rahul M. Patent Filings

Rao; Rahul M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rao; Rahul M..The latest application filed is for "scan chain wirelength optimization using q-learning based reinforcement learning".

Company Profile
2.37.44
  • Rao; Rahul M. - Bangalore IN
  • Rao; Rahul M - Bangalore IN
  • Rao; Rahul M. - Austin TX US
  • Rao; Rahul M. - Elmsford NY US
  • Rao; Rahul M. - Ann Arbor MI
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Scan Chain Wirelength Optimization Using Q-learning Based Reinforcement Learning
App 20220100936 - ABDUL; NAIJU KARIM ;   et al.
2022-03-31
Core pairing in multicore systems
Grant 10,831,620 - Dusanapudi , et al. November 10, 2
2020-11-10
Formal verification driven power modeling and design verification
Grant 10,354,028 - Haridass , et al. July 16, 2
2019-07-16
Cross-current power modelling using logic simulation
Grant 10,216,878 - Joseph , et al. Feb
2019-02-26
On The Fly Netlist Compression In Power Analysis
App 20180232469 - Joseph; Arun ;   et al.
2018-08-16
Fly Netlist Compression In Power Analysis
App 20180232470 - Joseph; Arun ;   et al.
2018-08-16
Cross-current power modelling using logic simulation
Grant 10,007,747 - Joseph , et al. June 26, 2
2018-06-26
On the fly netlist compression in power analysis
Grant 10,002,220 - Joseph , et al. June 19, 2
2018-06-19
On the fly netlist compression in power analysis
Grant 9,996,649 - Joseph , et al. June 12, 2
2018-06-12
Delayed equivalence identification
Grant 9,934,873 - Gajavelly , et al. April 3, 2
2018-04-03
Cross-current power modelling using logic simulation
Grant 9,916,406 - Joseph , et al. March 13, 2
2018-03-13
Core Pairing In Multicore Systems
App 20170364421 - Dusanapudi; Manoj ;   et al.
2017-12-21
Delayed Equivalence Identification
App 20170365362 - Gajavelly; Raj Kumar ;   et al.
2017-12-21
Formal Verification Driven Power Modeling And Design Verification
App 20170344678 - Haridass; Anand ;   et al.
2017-11-30
Cross-current Power Modelling Using Logic Simulation
App 20170337312 - Joseph; Arun ;   et al.
2017-11-23
Cross-current Power Modelling Using Logic Simulation
App 20170337311 - Joseph; Arun ;   et al.
2017-11-23
On The Fly Netlist Compression In Power Analysis
App 20170316119 - Joseph; Arun ;   et al.
2017-11-02
On The Fly Netlist Compression In Power Analysis
App 20170315605 - Joseph; Arun ;   et al.
2017-11-02
Cross-current power modelling using logic simulation
Grant 9,754,058 - Joseph , et al. September 5, 2
2017-09-05
Formal Verification Driven Power Modeling And Design Verification
App 20170235856 - Haridass; Anand ;   et al.
2017-08-17
Formal verification driven power modeling and design verification
Grant 9,697,306 - Haridass , et al. July 4, 2
2017-07-04
Cross-current Power Modelling Using Logic Simulation
App 20170132342 - Joseph; Arun ;   et al.
2017-05-11
Cross-current Power Modelling Using Logic Simulation
App 20170132343 - Joseph; Arun ;   et al.
2017-05-11
Addressing Early Mode Slack Fails By Book Decomposition
App 20160364518 - Madiraju; Mithula ;   et al.
2016-12-15
Addressing early mode slack fails by book decomposition
Grant 9,519,746 - Madiraju , et al. December 13, 2
2016-12-13
Formal verification driven power modeling and design verification
Grant 9,460,251 - Haridass , et al. October 4, 2
2016-10-04
Modified standard cells to address fast paths
Grant 9,280,630 - Lewis , et al. March 8, 2
2016-03-08
Usage-based temporal degradation estimation for memory elements
Grant 9,064,071 - Bansal , et al. June 23, 2
2015-06-23
Usage-based temporal degradation estimation for memory elements
Grant 9,058,448 - Bansal , et al. June 16, 2
2015-06-16
Estimating Delay Deterioration Due To Device Degradation In Integrated Circuits
App 20150154331 - Bansal; Aditya ;   et al.
2015-06-04
Estimating delay deterioration due to device degradation in integrated circuits
Grant 8,966,420 - Bansal , et al. February 24, 2
2015-02-24
Dual-cell Mtj Structure With Individual Access And Logical Combination Ability
App 20130258750 - KIM; JAE-JOON ;   et al.
2013-10-03
Estimating Delay Deterioration Due To Device Degradation In Integrated Circuits
App 20130254731 - Bansal; Aditya ;   et al.
2013-09-26
Estimating Delay Deterioration Due To Device Degradation In Integrated Circuits
App 20130253868 - BANSAL; ADITYA ;   et al.
2013-09-26
Enhanced static random access memory stability using asymmetric access transistors and design structure for same
Grant 8,526,219 - Bansal , et al. September 3, 2
2013-09-03
Performing logic functions on more than one memory cell within an array of memory cells
Grant 8,493,774 - Kuang , et al. July 23, 2
2013-07-23
Monitoring negative bias temperature instability (NBTI) and/or positive bias temperature instability (PBTI)
Grant 8,456,247 - Kim , et al. June 4, 2
2013-06-04
Usage-based Temporal Degradation Estimation For Memory Elements
App 20130138407 - Bansal; Aditya ;   et al.
2013-05-30
Usage-based Temporal Degradation Estimation For Memory Elements
App 20130138403 - Bansal; Aditya ;   et al.
2013-05-30
On-Chip Delay Measurement Through a Transistor Array
App 20130049791 - Jenkins; Keith A. ;   et al.
2013-02-28
Performing Logic Functions on More Than One Memory Cell Within an Array of Memory Cells
App 20120320689 - Kuang; Jente B. ;   et al.
2012-12-20
Monitoring Negative Bias Temperature Instability (nbti) And/or Positive Bias Temperature Instability (pbti)
App 20120182079 - Kim; Jae-Joon ;   et al.
2012-07-19
Enhanced Static Random Access Memory Stability Using Asymmetric Access Transistors and Design Structure for Same
App 20120185817 - Bansal; Aditya ;   et al.
2012-07-19
On-Chip Delay Measurement Through a Transistor Array
App 20120081141 - Jenkins; Keith A. ;   et al.
2012-04-05
Enhanced static random access memory stability using asymmetric access transistors and design structure for same
Grant 8,139,400 - Bansal , et al. March 20, 2
2012-03-20
Electronic circuit for measurement of transistor variability and the like
Grant 8,004,305 - Jenkins , et al. August 23, 2
2011-08-23
Static pulsed bus circuit and method having dynamic power supply rail selection
Grant 7,882,370 - Deogun , et al. February 1, 2
2011-02-01
Methods of operating an electronic circuit for measurement of transistor variability and the like
Grant 7,764,080 - Jenkins , et al. July 27, 2
2010-07-27
Memory circuit with decoupled read and write bit lines and improved write stability
Grant 7,746,709 - Joshi , et al. June 29, 2
2010-06-29
Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect
Grant 7,642,864 - Chuang , et al. January 5, 2
2010-01-05
Electronic Circuit For Measurement Of Transistor Variability And The Like
App 20090309625 - Jenkins; Keith A. ;   et al.
2009-12-17
Circuits And Design Structures For Monitoring Nbti (negative Bias Temperature Instability) Effect And/or Pbti (positive Bias Temperature Instability) Effect
App 20090189703 - Chuang; Ching-Te K. ;   et al.
2009-07-30
Enhanced Static Random Access Memory Stability Using Asymmetric Access Transistors And Design Structure For Same
App 20090185409 - Bansal; Aditya ;   et al.
2009-07-23
Method and circuit for measuring operating and leakage current of individual blocks within an array of test circuit blocks
Grant 7,550,987 - Acharyya , et al. June 23, 2
2009-06-23
Apparatus and method for determining the slew rate of a signal produced by an integrated circuit
Grant 7,548,822 - Chuang , et al. June 16, 2
2009-06-16
Memory Circuit with Decoupled Read and Write Bit Lines and Improved Write Stability
App 20090147592 - Joshi; Rajiv V. ;   et al.
2009-06-11
Techniques for improving write stability of memory with decoupled read and write bit lines
Grant 7,495,969 - Joshi , et al. February 24, 2
2009-02-24
Apparatus And Method For Determining The Slew Rate Of A Signal Produced By An Integrated Circuit
App 20090018787 - Chuang; Ching-Te K. ;   et al.
2009-01-15
Methods of Operating an Electronic Circuit for Measurement of Transistor Variability and the Like
App 20080315907 - Jenkins; Keith A. ;   et al.
2008-12-25
Electronic circuit for measurement of transistor variability and the like
Grant 7,439,755 - Jenkins , et al. October 21, 2
2008-10-21
Method and Circuit for Measuring Operating and Leakage Current of Individual Blocks Within an Array of Test Circuit Blocks
App 20080209285 - Acharyya; Dhruva J. ;   et al.
2008-08-28
Techniques For Improving Write Stability Of Memory With Decoupled Read And Write Bit Lines
App 20080181029 - Joshi; Rajiv V. ;   et al.
2008-07-31
Electronic Circuit for Measurement of Transistor Variability and the Like
App 20080180134 - Jenkins; Keith A. ;   et al.
2008-07-31
FINFET drive strength de-quantization using multiple orientation fins
App 20080121948 - Kim; Jae-Joon ;   et al.
2008-05-29
Static Pulsed Bus Circuit and Method Having Dynamic Power Supply Rail Selection
App 20080069558 - Deogun; Harmander Singh ;   et al.
2008-03-20
Multi-threshold complementary metal-oxide semiconductor (MTCMOS) bus circuit and method for reducing bus power consumption via pulsed standby switching
Grant 7,088,141 - Deogun , et al. August 8, 2
2006-08-08
Multi-threshold complementary metal-oxide semiconductor (MTCMOS) bus circuit and method for reducing bus power consumption via pulsed standby switching
App 20060082384 - Deogun; Harmander Singh ;   et al.
2006-04-20
Technique for mitigating gate leakage during a sleep state
Grant 6,791,361 - Alon , et al. September 14, 2
2004-09-14
Technique for mitigating gate leakage during a sleep state
App 20040113657 - Alon, Elad ;   et al.
2004-06-17

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