Rangasayee; Krishna

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rangasayee; Krishna.The latest application filed is for "programmable logic device for wireless local area network".

Company Profile

0.24.5

Rangasayee; Krishna - Mountain View CA
Rangasayee; Krishna - Pleasanton CA
Rangasayee; Krishna - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Apparatus and method for routing of signals Grant 8,912,831 - Veenstra , et al. December 16, 2	2014-12-16
Apparatus and method for routing of signals Grant 8,233,577 - Veenstra , et al. July 31, 2	2012-07-31
Apparatus and method for low power routing of signals in a low voltage differential signaling system Grant 7,593,499 - Veenstra , et al. September 22, 2	2009-09-22
Programmable logic device for wireless local area network Grant 7,142,557 - Dhir , et al. November 28, 2	2006-11-28
Apparatus and method for low power routing of signals in a Low Voltage Differential Signaling system Grant 6,956,920 - Veenstra , et al. October 18, 2	2005-10-18
Configurable communication integrated circuit Grant 6,957,283 - Dhir , et al. October 18, 2	2005-10-18
Programmable logic device for wireless local area network App 20050084076 - Dhir, Amit ; et al.	2005-04-21
Enhanced embedded logic analyzer Grant 6,704,889 - Veenstra , et al. March 9, 2	2004-03-09
Apparatus and method for programming a set of programmable logic devices in parallel Grant 6,625,796 - Rangasayee , et al. September 23, 2	2003-09-23
Fully programmable I/O pin with memory Grant 6,577,157 - Cheung , et al. June 10, 2	2003-06-10
Configurable communication integrated circuit App 20030023762 - Dhir, Amit ; et al.	2003-01-30
Enhanced embedded logic analyzer App 20020194543 - Veenstra, Kerry ; et al.	2002-12-19
Enhanced embedded logic analyzer Grant 6,460,148 - Veenstra , et al. October 1, 2	2002-10-01
Programmable logic device input/output architecture with power bus segmentation for multiple I/O standards Grant 6,377,069 - Veenstra , et al. April 23, 2	2002-04-23
Enhanced embedded logic analyzer App 20010037477 - Veenstra, Kerry ; et al.	2001-11-01
Programmable logic device incorporating function blocks operable as wide-shallow RAM Grant 6,292,017 - Rangasayee September 18, 2	2001-09-18
Enhanced embedded logic analyzer Grant 6,286,114 - Veenstra , et al. September 4, 2	2001-09-04
Programmable logic device incorporating function blocks operable as wide-shallow ram App 20010013793 - Rangasayee, Krishna	2001-08-16
Programmable logic device having an integrated phase lock loop Grant 6,272,646 - Rangasayee , et al. August 7, 2	2001-08-07
Enhanced embedded logic analyzer Grant 6,247,147 - Beenstra , et al. June 12, 2	2001-06-12
Configuration eprom with programmable logic Grant 6,198,303 - Rangasayee March 6, 2	2001-03-06
Integrated circuit incorporating a programmable cross-bar switch Grant 6,181,159 - Rangasayee January 30, 2	2001-01-30
Programmable logic device with selectable schmitt-triggered and threshold-triggered buffers Grant 6,163,166 - Bielby , et al. December 19, 2	2000-12-19
Programmable logic device incorporating function blocks operable as wide-shallow RAM Grant 6,104,208 - Rangasayee August 15, 2	2000-08-15
Programmable logic device architecture incorporating a dedicated cross-bar switch Grant 6,060,903 - Rangasayee , et al. May 9, 2	2000-05-09
Memory cells configurable as CAM or RAM in programmable logic devices Grant 6,058,452 - Rangasayee , et al. May 2, 2	2000-05-02
Memory cells configurable as CAM or RAM in programmable logic devices Grant 5,940,852 - Rangasayee , et al. August 17, 1	1999-08-17
Method and apparatus for generating an asynchronously clocked signal in a synchronously clocked programmable device Grant 5,638,008 - Rangasayee , et al. June 10, 1	1997-06-10

Company Registrations

SEC

0001550174

Rangasayee Krishna

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