RANGARAJAN; Bharat Kumar

Patent Applications and Registrations

Patent applications and USPTO patent grants for RANGARAJAN; Bharat Kumar.The latest application filed is for "core voltage regulator energy-aware task scheduling".

Company Profile

12.6.12

RANGARAJAN; Bharat Kumar - BANGALORE IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Core Voltage Regulator Energy-aware Task Scheduling App 20220222112 - DIBBAD; Vijayakumar Ashok ; et al.	2022-07-14
Processor Security Mode Based SoC Infrastructure Power Management App 20220206559 - RANGARAJAN; Bharat Kumar ; et al.	2022-06-30
On-die Voltage-frequency Security Monitor App 20210357502 - RANGARAJAN; Bharat Kumar ; et al.	2021-11-18
Selective coupling of memory to voltage rails for different operating modes Grant 11,169,593 - Srinivas , et al. November 9, 2	2021-11-09
System Physical Address Size Aware Cache Memory App 20210263581 - RANGARAJAN; Bharat Kumar ; et al.	2021-08-26
Method And System For Improving Rock Bottom Sleep Current Of Processor Memories App 20210191500 - RANGARAJAN; Bharat Kumar ; et al.	2021-06-24
Method And System For Waking Up A Cpu From A Power-saving Mode App 20210157382 - Rangarajan; Bharat Kumar ; et al.	2021-05-27
Asymmetric memory tag access and design Grant 10,831,667 - Rangarajan , et al. November 10, 2	2020-11-10
Dynamic Memory Power Management App 20200278739 - SRINIVAS; Raghavendra ; et al.	2020-09-03
Selective coupling of memory to voltage rails based on operating mode of processor Grant 10,691,195 - Srinivas , et al.	2020-06-23
Method and apparatus for automatic switch to retention mode based on architectural clock gating Grant 10,664,006 - Rangarajan , et al.	2020-05-26
Asymmetric Memory Tag Access And Design App 20200133862 - RANGARAJAN; Bharat Kumar ; et al.	2020-04-30
Grouping central processing unit memories based on dynamic clock and voltage scaling timing to improve dynamic/leakage power using array power multiplexers Grant 10,466,766 - Arimilli , et al. No	2019-11-05
Dynamic Memory Power Management App 20190265778 - SRINIVAS; Raghavendra ; et al.	2019-08-29
Method And Apparatus For Automatic Switch To Retention Mode Based On Architectural Clock Gating App 20190212768 - RANGARAJAN; Bharat Kumar ; et al.	2019-07-11
Grouping Central Processing Unit Memories Based On Dynamic Clock And Voltage Scaling Timing To Improve Dynamic/leakage Power Using Array Power Multiplexers App 20190138079 - ARIMILLI; Rajesh ; et al.	2019-05-09
Memory leakage power savings Grant 10,248,558 - Rangarajan , et al.	2019-04-02
Memory Leakage Power Savings App 20190065359 - Rangarajan; Bharat Kumar ; et al.	2019-02-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.