Rangaraj; Sudarshan V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rangaraj; Sudarshan V..The latest application filed is for "packaged integrated circuit and method of forming thereof".

Company Profile

0.3.5

Rangaraj; Sudarshan V. - Chandler AZ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Embedded capacitors for reducing package cracking Grant 7,719,109 - Modi , et al. May 18, 2	2010-05-18
Method of forming a microelectronic package using control of die and substrate differential expansions and microelectronic package formed according to the method Grant 7,585,693 - Frutschy , et al. September 8, 2	2009-09-08
Packaged Integrated Circuit And Method Of Forming Thereof App 20090065931 - Rangaraj; Sudarshan V. ; et al.	2009-03-12
Embedded capacitors for reducing package cracking App 20080096310 - Modi; Mitul ; et al.	2008-04-24
Microelectronic assembly having a periphery seal around a thermal interface material App 20080001282 - Modi; Mitul ; et al.	2008-01-03
Method and system for performing die attach using a flame Grant 7,288,472 - Frutschy , et al. October 30, 2	2007-10-30
Method of forming a microelectronic package using control of die and substrate differential expansions and microelectronic package formed according to the method App 20070231952 - Frutschy; Kristopher J. ; et al.	2007-10-04
Method and system for performing die attach using a flame App 20060134830 - Frutschy; Kris J. ; et al.	2006-06-22

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