Randazzo; Todd A.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Randazzo; Todd A..The latest application filed is for "neutron detector cell efficiency".

Company Profile

0.30.14

Randazzo; Todd A. - Morristown NJ US
Randazzo; Todd A. - Colorado Springs CO
Randazzo; Todd A. - Plymouth MN
Randazzo; Todd A. - Mound MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Neutron detector cell efficiency Grant 8,399,845 - Fechner , et al. March 19, 2	2013-03-19
Resistive voltage-down regulator for integrated circuit receivers Grant 8,315,588 - Randazzo November 20, 2	2012-11-20
Neutron detector with wafer-to-wafer bonding Grant 8,310,021 - Larsen , et al. November 13, 2	2012-11-13
Neutron Detector Cell Efficiency App 20120228513 - Fechner; Paul S. ; et al.	2012-09-13
Neutron Detector With Wafer-to-wafer Bonding App 20120012957 - Larsen; Bradley J. ; et al.	2012-01-19
Heavy Ion Upset Hardened Floating Body SRAM Cells App 20100200918 - Larsen; Bradley J. ; et al.	2010-08-12
Planar Metal-Insulator-Metal Circuit Element and Method for Planar Integration of Same App 20100006912 - Larsen; Bradley J. ; et al.	2010-01-14
Use of a known common-mode voltage for input overvoltage protection in pseudo-differential receivers Grant 7,457,090 - Randazzo November 25, 2	2008-11-25
Method and apparatus for summing DC voltages Grant 7,180,360 - Randazzo February 20, 2	2007-02-20
Analog capacitor in dual damascene process Grant 7,176,082 - Randazzo , et al. February 13, 2	2007-02-13
Method and apparatus for summing DC voltages App 20060103447 - Randazzo; Todd A.	2006-05-18
Use of a known common-mode voltage for input overvoltage protection in pseudo-differential receivers App 20060103999 - Randazzo; Todd A.	2006-05-18
Resistive voltage-down regulator for integrated circuit receivers App 20050245226 - Randazzo, Todd A.	2005-11-03
Programmable transmit SCSI equalization Grant 6,931,560 - Porter , et al. August 16, 2	2005-08-16
Level shifter reference generator Grant 6,924,689 - Randazzo , et al. August 2, 2	2005-08-02
Analog capacitor in dual damascene process App 20050042818 - Randazzo, Todd A. ; et al.	2005-02-24
Low voltage breakdown element for ESD trigger device Grant 6,855,586 - Walker , et al. February 15, 2	2005-02-15
CMOS varactor with constant dC/dV characteristic Grant 6,825,546 - Walker , et al. November 30, 2	2004-11-30
Analog capacitor in dual damascene process Grant 6,822,282 - Randazzo , et al. November 23, 2	2004-11-23
Method and apparatus for determining temperature of a semiconductor wafer during fabrication thereof Grant 6,794,310 - Miller , et al. September 21, 2	2004-09-21
Low voltage breakdown element for ESD trigger device App 20040104436 - Walker, John de Q. ; et al.	2004-06-03
Low voltage breakdown element for ESD trigger device Grant 6,710,990 - Walker , et al. March 23, 2	2004-03-23
Level shifter reference generator App 20030227313 - Randazzo, Todd A. ; et al.	2003-12-11
Analog capacitor in dual damascene process App 20030176035 - Randazzo, Todd A. ; et al.	2003-09-18
Control circuit for power Grant 6,621,299 - Randazzo , et al. September 16, 2	2003-09-16
Voltage level shifter Grant 6,614,283 - Wright , et al. September 2, 2	2003-09-02
Low voltage breakdown element for ESD trigger device App 20030137789 - Walker, John de Q. ; et al.	2003-07-24
Method of forming analog capacitor dual damascene process Grant 6,596,579 - Randazzo , et al. July 22, 2	2003-07-22
Linear capacitor and process for making same Grant 6,545,305 - Randazzo April 8, 2	2003-04-08
High speed input App 20030042943 - Randazzo, Todd A. ; et al.	2003-03-06
Semiconductor device with a pair of transistors having dual work function gate electrodes Grant 6,514,824 - Randazzo , et al. February 4, 2	2003-02-04
Swapped drain structures for electrostatic discharge protection App 20020055219 - Randazzo, Todd A.	2002-05-09
Interconnect-integrated metal-insulator-metal capacitor and method of fabricating same Grant 6,342,734 - Allman , et al. January 29, 2	2002-01-29
MeV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor Grant 6,316,817 - Seliskar , et al. November 13, 2	2001-11-13
Semiconductor device with a pair of transistors having dual work function gate electrodes Grant 6,211,555 - Randazzo , et al. April 3, 2	2001-04-03
NMOS electrostatic discharge protection device and method for CMOS integrated circuit Grant 6,063,672 - Miller , et al. May 16, 2	2000-05-16
Use of MEV implantation to form vertically modulated N+ buried layer in an NPN bipolar transistor Grant 5,858,828 - Seliskar , et al. January 12, 1	1999-01-12
Simple BICMOS process for creation of low trigger voltage SCR and zener diode pad protection Grant 5,821,572 - Walker , et al. October 13, 1	1998-10-13
Process for fabricating a moderate-depth diffused emitter bipolar transistor in a BICMOS device without using an additional mask Grant 5,780,329 - Randazzo , et al. July 14, 1	1998-07-14
Drain excluded EPROM cell Grant 5,661,687 - Randazzo August 26, 1	1997-08-26
Non-volatile memory which is programmable from a power source Grant 5,648,930 - Randazzo July 15, 1	1997-07-15
Input/output transistors with optimized ESD protection Grant 5,493,142 - Randazzo , et al. February 20, 1	1996-02-20
Integration of high performance submicron CMOS and dual-poly non-volatile memory devices using a third polysilicon layer Grant 5,340,764 - Larsen , et al. August 23, 1	1994-08-23

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