Ranade; Pushkar

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ranade; Pushkar.The latest application filed is for "semiconductor structure with multiple transistors having various threshold voltages and method of fabrication thereto".

Company Profile

2.94.66

Ranade; Pushkar - Los Gatos CA
Ranade; Pushkar - San Jose CA
Ranade; Pushkar - Hillsboro OR
Ranade; Pushkar - Berkeley CA
Ranade, Pushkar - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Advanced transistors with punch through suppression Grant 10,325,986 - Shifren , et al.	2019-06-18
Semiconductor structure with multiple transistors having various threshold voltages Grant 10,217,838 - Zhao , et al. Feb	2019-02-26
Semiconductor Structure With Multiple Transistors Having Various Threshold Voltages and Method of Fabrication Thereto App 20180261683 - Zhao; Dalong ; et al.	2018-09-13
Semiconductor structure with multiple transistors having various threshold voltages Grant 10,014,387 - Zhao , et al. July 3, 2	2018-07-03
Buried channel deeply depleted channel transistor Grant 9,991,300 - Bakhishev , et al. June 5, 2	2018-06-05
Transistor with threshold voltage set notch and method of fabrication thereof Grant 9,922,977 - Arghavani , et al. March 20, 2	2018-03-20
Low power semiconductor transistor structure and method of fabrication thereof Grant 9,865,596 - Shifren , et al. January 9, 2	2018-01-09
Active regions with compatible dielectric layers Grant 9,847,420 - Ranade December 19, 2	2017-12-19
Buried Channel Deeply Depleted Channel Transistor App 20170323916 - Bakhishev; Teymur ; et al.	2017-11-09
Semiconductor structure with multiple transistors having various threshold voltages Grant 9,812,550 - Zhao , et al. November 7, 2	2017-11-07
Reducing or eliminating pre-amorphization in transistor manufacture Grant 9,793,172 - Scudder , et al. October 17, 2	2017-10-17
Buried channel deeply depleted channel transistor Grant 9,786,703 - Bakhishev , et al. October 10, 2	2017-10-10
Active Regions With Compatible Dielectric Layers App 20170207336 - Ranade; Pushkar	2017-07-20
Semiconductor Structure with Multiple Transistors Having Various Threshold Voltages App 20170141209 - Zhao; Dalong ; et al.	2017-05-18
Active regions with compatible dielectric layers Grant 9,646,822 - Ranade May 9, 2	2017-05-09
Active Regions With Compatible Dielectric Layers App 20170062593 - Ranade; Pushkar	2017-03-02
Advanced Transistors with Punch Through Suppression App 20170040419 - Shifren; Lucian ; et al.	2017-02-09
Reducing or Eliminating Pre-Amorphization in Transistor Manufacture App 20170040225 - Scudder; Lance ; et al.	2017-02-09
Buried Channel Deeply Depleted Channel Transistor App 20170025457 - Bakhishev; Teymur ; et al.	2017-01-26
Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof App 20170012044 - Shifren; Lucian ; et al.	2017-01-12
Active regions with compatible dielectric layers Grant 9,515,142 - Ranade December 6, 2	2016-12-06
Reducing or eliminating pre-amorphization in transistor manufacture Grant 9,514,940 - Scudder , et al. December 6, 2	2016-12-06
CMOS gate stack structures and processes Grant 9,508,728 - Hoffmann , et al. November 29, 2	2016-11-29
Advanced transistors with punch through suppression Grant 9,508,800 - Shifren , et al. November 29, 2	2016-11-29
Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof App 20160336318 - Arghavani; Reza ; et al.	2016-11-17
Low power semiconductor transistor structure and method of fabrication thereof Grant 9,496,261 - Shifren , et al. November 15, 2	2016-11-15
Active Regions With Compatible Dielectric Layers App 20160315148 - Ranade; Pushkar	2016-10-27
Buried channel deeply depleted channel transistor Grant 9,478,571 - Bakhishev , et al. October 25, 2	2016-10-25
CMOS Structures and Processes Based on Selective Thinning App 20160307907 - Thompson; Scott E. ; et al.	2016-10-20
Reducing Or Eliminating Pre-amorphization In Transistor Manufacture App 20160268133 - Scudder; Lance S. ; et al.	2016-09-15
Transistor with threshold voltage set notch and method of fabrication thereof Grant 9,418,987 - Arghavani , et al. August 16, 2	2016-08-16
Method for fabricating multiple transistor devices on a substrate with varying threshold voltages Grant 9,406,567 - Shifren , et al. August 2, 2	2016-08-02
Epitaxial Channel Transistors and Die With Diffusion Doped Channels App 20160211346 - Shifren; Lucian ; et al.	2016-07-21
Active regions with compatible dielectric layers Grant 9,397,165 - Ranade July 19, 2	2016-07-19
CMOS structures and processes based on selective thinning Grant 9,391,076 - Thompson , et al. July 12, 2	2016-07-12
Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same Grant 9,385,047 - Zhao , et al. July 5, 2	2016-07-05
Advanced Transistors with Punch Through Suppression App 20160181370 - Shifren; Lucian ; et al.	2016-06-23
Active Regions With Compatible Dielectric Layers App 20160172459 - Ranade; Pushkar	2016-06-16
Method for fabricating a transistor with reduced junction leakage current Grant 9,368,624 - Thompson , et al. June 14, 2	2016-06-14
Semiconductor Structure with Multiple Transistors Having Various Threshold Voltages App 20160163823 - Zhao; Dalong ; et al.	2016-06-09
CMOS Gate Stack Structures and Processes App 20160141292 - Hoffmann; Thomas ; et al.	2016-05-19
Semiconductor structure with multiple transistors having various threshold voltages Grant 9,299,698 - Zhao , et al. March 29, 2	2016-03-29
Active regions with compatible dielectric layers Grant 9,287,364 - Ranade March 15, 2	2016-03-15
CMOS gate stack structures and processes Grant 9,281,248 - Hoffmann , et al. March 8, 2	2016-03-08
Advanced transistors with punch through suppression Grant 9,263,523 - Shifren , et al. February 16, 2	2016-02-16
Semiconductor structure and method of fabrication thereof with mixed metal types Grant 9,224,733 - Shifren , et al. December 29, 2	2015-12-29
Advanced Transistors With Threshold Voltage Set Dopant Structures App 20150340460 - Shifren; Lucian ; et al.	2015-11-26
High uniformity screen and epitaxial layers for CMOS devices Grant 9,196,727 - Thompson , et al. November 24, 2	2015-11-24
High Uniformity Screen and Epitaxial Layers for CMOS Devices App 20150333144 - Thompson; Scott E. ; et al.	2015-11-19
Integrated Circuits Having a Plurality of High-K Metal Gate FETs with Various Combinations of Channel Foundation Structure and Gate Stack Structure and Methods of Making Same App 20150287645 - Zhao; Dalong ; et al.	2015-10-08
Semiconductor devices with dopant migration suppression and method of fabrication thereof Grant 9,112,057 - Pradhan , et al. August 18, 2	2015-08-18
Semiconductor structure with improved channel stack and method for fabrication thereof Grant 9,111,785 - Gregory , et al. August 18, 2	2015-08-18
Semiconductor structure with reduced junction leakage and method of fabrication thereof Grant 9,105,711 - Wang , et al. August 11, 2	2015-08-11
Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same Grant 9,093,550 - Zhao , et al. July 28, 2	2015-07-28
Active Regions With Compatible Dielectric Layers App 20150179742 - Ranade; Pushkar	2015-06-25
Deeply depleted MOS transistors having a screening layer and methods thereof Grant 9,041,126 - Hoffmann , et al. May 26, 2	2015-05-26
Source/drain extension control for advanced transistors Grant 9,006,843 - Ranade , et al. April 14, 2	2015-04-14
Semiconductor structure with substitutional boron and method for fabrication thereof Grant 8,999,861 - Scudder , et al. April 7, 2	2015-04-07
High Uniformity Screen And Epitaxial Layers For Cmos Devices App 20150061012 - Thompson; Scott E. ; et al.	2015-03-05
Electronic device with controlled threshold voltage Grant 8,963,249 - Shifren , et al. February 24, 2	2015-02-24
Reducing or eliminating pre-amorphization in transistor manufacture Grant 8,937,005 - Scudder , et al. January 20, 2	2015-01-20
Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer Grant 8,916,937 - Hoffmann , et al. December 23, 2	2014-12-23
Transistor having reduced junction leakage and methods of forming thereof Grant 8,883,600 - Thompson , et al. November 11, 2	2014-11-11
Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom Grant 8,877,619 - Thompson , et al. November 4, 2	2014-11-04
Method for minimizing defects in a semiconductor substrate due to ion implantation Grant 8,858,818 - Ranade , et al. October 14, 2	2014-10-14
Transistor With Threshold Voltage Set Notch And Method Of Fabrication Thereof App 20140284722 - Arghavani; Reza ; et al.	2014-09-25
Monitoring and measurement of thin film layers Grant 8,796,048 - Thompson , et al. August 5, 2	2014-08-05
Method for substrate preservation during transistor fabrication Grant 8,778,786 - Scudder , et al. July 15, 2	2014-07-15
Transistor with threshold voltage set notch and method of fabrication thereof Grant 8,759,872 - Arghavani , et al. June 24, 2	2014-06-24
Advanced Transistors With Punch Through Suppression App 20140167156 - Shifren; Lucian ; et al.	2014-06-19
Source/drain Extension Control For Advanced Transistors App 20140167157 - Ranade; Pushkar ; et al.	2014-06-19
Electronic device with controlled threshold voltage Grant 8,748,986 - Shifren , et al. June 10, 2	2014-06-10
CMOS gate stack structures and processes Grant 8,735,987 - Hoffmann , et al. May 27, 2	2014-05-27
Semiconductor Structure With Reduced Junction Leakage And Method Of Fabrication Thereof App 20140103406 - Wang; Lingquan ; et al.	2014-04-17
Source/drain extension control for advanced transistors Grant 8,686,511 - Ranade , et al. April 1, 2	2014-04-01
Deeply Depleted Mos Transistors Having A Screening Layer And Methods Thereof App 20140084385 - Hoffmann; Thomas ; et al.	2014-03-27
Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer Grant 8,653,604 - Hoffmann , et al. February 18, 2	2014-02-18
Semiconductor Structure And Method Of Fabrication Thereof With Mixed Metal Types App 20140035060 - Shifren; Lucian ; et al.	2014-02-06
Reducing Or Eliminating Pre-amorphization In Transistor Manufacture App 20140038386 - Scudder; Lance S. ; et al.	2014-02-06
Semiconductor structure with reduced junction leakage and method of fabrication thereof Grant 8,637,955 - Wang , et al. January 28, 2	2014-01-28
Source/drain Extension Control For Advanced Transistors App 20140015067 - Ranade; Pushkar ; et al.	2014-01-16
Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer Grant 8,629,016 - Hoffmann , et al. January 14, 2	2014-01-14
Semiconductor Structure With Multiple Transistors Having Various Threshold Voltages And Method Of Fabrication Thereof App 20140001571 - Zhao; Dalong ; et al.	2014-01-02
CMOS structures and processes based on selective thinning Grant 8,614,128 - Thompson , et al. December 24, 2	2013-12-24
Low Power Semiconductor Transistor Structure And Method Of Fabrication Thereof App 20130328129 - Shifren; Lucian ; et al.	2013-12-12
Semiconductor Structure With Improved Channel Stack And Method For Fabrication Thereof App 20130313652 - Gregory; Paul E. ; et al.	2013-11-28
Reducing or eliminating pre-amorphization in transistor manufacture Grant 8,569,156 - Scudder , et al. October 29, 2	2013-10-29
Semiconductor structure and method of fabrication thereof with mixed metal types Grant 8,569,128 - Shifren , et al. October 29, 2	2013-10-29
Source/drain extension control for advanced transistors Grant 8,563,384 - Ranade , et al. October 22, 2	2013-10-22
Low power semiconductor transistor structure and method of fabrication thereof Grant 8,530,286 - Shifren , et al. September 10, 2	2013-09-10
Semiconductor structure with improved channel stack and method for fabrication thereof Grant 8,525,271 - Gregory , et al. September 3, 2	2013-09-03
Advanced Transistors With Punch Through Suppression App 20130181298 - Shifren; Lucian ; et al.	2013-07-18
Source/drain Extension Control For Advanced Transistors App 20130161743 - Ranade; Pushkar ; et al.	2013-06-27
Advanced transistors with punch through suppression Grant 8,421,162 - Shifren , et al. April 16, 2	2013-04-16
Source/drain extension control for advanced transistors Grant 8,404,551 - Ranade , et al. March 26, 2	2013-03-26
Ultra-abrupt semiconductor junction profile Grant 8,394,687 - Ranade , et al. March 12, 2	2013-03-12
Semiconductor Structure With Improved Channel Stack And Method For Fabrication Thereof App 20120223389 - Gregory; Paul E. ; et al.	2012-09-06
Source/drain Extension Control For Advanced Transistors App 20120139051 - Ranade; Pushkar ; et al.	2012-06-07
Method For Minimizing Defects In A Semiconductor Substrate Due To Ion Implantation App 20120083132 - Ranade; Pushkar ; et al.	2012-04-05
Semiconductor Structure And Method Of Fabrication Thereof With Mixed Metal Types App 20110309450 - Shifren; Lucian ; et al.	2011-12-22
Transistor With Threshold Voltage Set Notch And Method Of Fabrication Thereof App 20110309447 - Arghavani; Reza ; et al.	2011-12-22
Low Power Semiconductor Transistor Structure And Method Of Fabrication Thereof App 20110248352 - Shifren; Lucian ; et al.	2011-10-13
Advanced Transistors With Punch Through Suppression App 20110121404 - Shifren; Lucian ; et al.	2011-05-26
Advanced Transistors with Threshold Voltage Set Dopant Structures App 20110079861 - Shifren; Lucian ; et al.	2011-04-07
Method of forming CMOS transistors with dual-metal silicide formed through the contact openings Grant 7,861,406 - Lodha , et al. January 4, 2	2011-01-04
Metal and alloy silicides on a single silicon wafer Grant 7,750,471 - Ranade July 6, 2	2010-07-06
Methods of forming improved EPI fill on narrow isolation bounded source/drain regions and structures formed thereby Grant 7,691,752 - Ranade , et al. April 6, 2	2010-04-06
CMOS device with dual-epi channels and self-aligned contacts Grant 7,598,142 - Ranade , et al. October 6, 2	2009-10-06
Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures Grant 7,566,938 - Cabral, Jr. , et al. July 28, 2	2009-07-28
Ultra-abrupt semiconductor junction profile App 20090090982 - Ranade; Pushkar ; et al.	2009-04-09
Metal and alloy silicides on a single silicon wafer App 20090001588 - Ranade; Pushkar	2009-01-01
Methods Of Forming Improved Epi Fill On Narrow Isolation Bounded Source/drain Regions And Structures Formed Thereby App 20080237742 - Ranade; Pushkar ; et al.	2008-10-02
Methods Of Forming Improved Epi Fill On Narrow Isolation Bounded Source/drain Regions And Structures Formed Thereby App 20080237741 - Ranade; Pushkar ; et al.	2008-10-02
Ultra-abrupt Semiconductor Junction Profile App 20080237661 - Ranade; Pushkar ; et al.	2008-10-02
Method Of Forming Cmos Transistors With Dual-metal Silicide Formed Through The Contact Openings And Structures Formed Thereby App 20080237603 - Lodha; Saurabh ; et al.	2008-10-02
CMOS device with dual-EPI channels and self-aligned contacts App 20080227250 - Ranade; Pushkar ; et al.	2008-09-18
Active regions with compatible dielectric layers App 20080121932 - Ranade; Pushkar	2008-05-29
Dual work function CMOS gate technology based on metal interdiffusion Grant 7,141,858 - Polishchuk , et al. November 28, 2	2006-11-28
Method to produce highly doped polysilicon thin films Grant 7,138,307 - Ranade , et al. November 21, 2	2006-11-21
Methods of optimization of implant conditions to minimize channeling and structures formed thereby App 20060202267 - Ranade; Pushkar ; et al.	2006-09-14
Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures App 20060138603 - Cabral; Cyril JR. ; et al.	2006-06-29
Methods of optimization of implant conditions to minimize channeling and structures formed thereby App 20060084248 - Ranade; Pushkar ; et al.	2006-04-20
Method to produce highly doped polysilicon thin films App 20060030109 - Ranade; Pushkar ; et al.	2006-02-09
Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures Grant 6,982,230 - Cabral, Jr. , et al. January 3, 2	2006-01-03
Dual work function CMOS gate technology based on metal interdiffusion App 20040238859 - Polishchuk, Igor ; et al.	2004-12-02
Dual work function CMOS gate technology based on metal interdiffusion Grant 6,794,234 - Polishchuk , et al. September 21, 2	2004-09-21
Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures App 20040092073 - Cabral, Cyril JR. ; et al.	2004-05-13
Dual work function CMOS gate technology based on metal interdiffusion App 20030180994 - Polishchuk, Igor ; et al.	2003-09-25