Ramsbey; Mark

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ramsbey; Mark.The latest application filed is for "resistive change elements using passivating interface gaps and methods for making same".

Company Profile

5.34.20

Ramsbey; Mark - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Split gate charge trapping memory cells having different select gate and memory gate heights Grant 11,450,680 - Chen , et al. September 20, 2	2022-09-20
Resistive change elements using passivating interface gaps and methods for making same Grant 11,258,023 - Ramsbey , et al. February 22, 2	2022-02-22
Resistive Change Elements Using Passivating Interface Gaps And Methods For Making Same App 20220045290 - RAMSBEY; Mark ; et al.	2022-02-10
Split Gate Charge Trapping Memory Cells Having Different Select Gate And Memory Gate Heights App 20210104533 - Chen; Chun ; et al.	2021-04-08
Memory first process flow and device Grant 10,818,761 - Fang , et al. October 27, 2	2020-10-27
Split gate charge trapping memory cells having different select gate and memory gate heights Grant 10,777,568 - Chen , et al. Sept	2020-09-15
Memory First Process Flow and Device App 20190386109 - Fang; Shenqing ; et al.	2019-12-19
Memory first process flow and device Grant 10,403,731 - Fang , et al. Sep	2019-09-03
Memory First Process Flow and Device App 20180366551 - Fang; Shenqing ; et al.	2018-12-20
Three dimensional capacitor Grant 10,141,393 - Ramsbey , et al. Nov	2018-11-27
Memory first process flow and device Grant 10,014,380 - Fang , et al. July 3, 2	2018-07-03
Charge trapping split gate embedded flash memory and associated methods Grant 9,922,833 - Ramsbey , et al. March 20, 2	2018-03-20
Memory first process flow and device Grant 9,917,166 - Fang , et al. March 13, 2	2018-03-13
Split Gate Charge Trapping Memory Cells Having Different Select Gate and Memory Gate Heights App 20170194343 - Chen; Chun ; et al.	2017-07-06
Memory First Process Flow and Device App 20170141201 - Fang; Shenqing ; et al.	2017-05-18
Use disposable gate cap to form transistors, and split gate charge trapping memory cells Grant 9,590,079 - Chen , et al. March 7, 2	2017-03-07
Memory First Process Flow and Device App 20160293720 - Fang; Shenqing ; et al.	2016-10-06
Gate formation memory by planarization Grant 9,368,644 - Fang , et al. June 14, 2	2016-06-14
Memory first process flow and device Grant 9,368,606 - Fang , et al. June 14, 2	2016-06-14
Charge Trapping Split Gate Embedded Flash Memory And Associated Methods App 20160111292 - RAMSBEY; Mark ; et al.	2016-04-21
Memory gate landing pad made from dummy features Grant 9,209,197 - Ramsbey , et al. December 8, 2	2015-12-08
Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells App 20150287812 - Chen; Chun ; et al.	2015-10-08
Process charging protection for split gate charge trapping flash Grant 8,816,438 - Chen , et al. August 26, 2	2014-08-26
Process Charging Protection for Split Gate Charge Trapping Flash App 20140167135 - CHEN; Chun ; et al.	2014-06-19
Charge Trapping Device with Improved Select Gate to Memory Gate Isoloation App 20140167136 - RAMSBEY; Mark ; et al.	2014-06-19
Memory First Process Flow and Device App 20140167140 - FANG; Shenqing ; et al.	2014-06-19
Charge Trapping Split Gate Embedded Flash Memory and Associated Methods App 20140167141 - RAMSBEY; Mark ; et al.	2014-06-19
Three Dimensional Capacitor App 20140167220 - RAMSBEY; Mark ; et al.	2014-06-19
Use Disposable Gate Cap to Form Transistors, and Split Gate Charge Trapping Memory Cells App 20140167142 - Chen; Chun ; et al.	2014-06-19
Memory Gate Landing Pad Made From Dummy Features App 20140167128 - RAMSBEY; Mark ; et al.	2014-06-19
Charge Trapping Split Gate Device and Method of Fabricating Same App 20140170843 - CHEN; Chun ; et al.	2014-06-19
Method of forming narrowly spaced flash memory contact openings and lithography masks Grant 7,507,661 - Lingunis , et al. March 24, 2	2009-03-24
LDC implant for mirrorbit to improve Vt roll-off and form sharper junction Grant 7,176,113 - Wong , et al. February 13, 2	2007-02-13
Method of formation of gate stack spacer and charge storage materials having reduced hydrogen content in charge trapping dielectric flash memory device Grant 7,163,860 - Kamal , et al. January 16, 2	2007-01-16
PECVD silicon-rich oxide layer for reduced UV charging Grant 7,060,554 - Ngo , et al. June 13, 2	2006-06-13
ONO fabrication process for increasing oxygen content at bottom oxide-substrate interface in flash memory devices Grant 7,033,957 - Shiraiwa , et al. April 25, 2	2006-04-25
Method of forming narrowly spaced flash memory contact openings and lithography masks App 20060035459 - Lingunis; Emmanuil H. ; et al.	2006-02-16
Bitline implant utilizing dual poly Grant 6,989,320 - Qian , et al. January 24, 2	2006-01-24
Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices Grant 6,989,319 - Ramsbey , et al. January 24, 2	2006-01-24
Bitline implant utilizing dual poly App 20050255651 - Qian, Weidong ; et al.	2005-11-17
Flash memory device and method of fabrication thereof including a bottom oxide layer with two regions with different concentrations of nitrogen Grant 6,958,511 - Halliyal , et al. October 25, 2	2005-10-25
Method of fabricating a planar structure charge trapping memory cell array with rectangular gates and reduced bit line resistance Grant 6,855,608 - Ramsbey , et al. February 15, 2	2005-02-15
PECVD silicon-rich oxide layer for reduced UV charging App 20050006712 - Ngo, Minh Van ; et al.	2005-01-13
Diode fabrication for ESD/EOS protection Grant 6,770,938 - Fliesler , et al. August 3, 2	2004-08-03
Nitride barrier layer for protection of ONO structure from top oxide loss in fabrication of SONOS flash memory Grant 6,680,509 - Wu , et al. January 20, 2	2004-01-20
Nitride barrier layer for protection of ONO structure from top oxide loss in a fabrication of SONOS flash memory Grant 6,440,797 - Wu , et al. August 27, 2	2002-08-27
Process for fabricating high density memory cells using a polysilicon hard mask Grant 6,436,766 - Rangarajan , et al. August 20, 2	2002-08-20
Nitrogen implant after bit-line formation for ONO flash memory devices Grant 6,403,420 - Yang , et al. June 11, 2	2002-06-11
Process for fabricating high density memory cells using a metallic hard mask Grant 6,399,446 - Rangarajan , et al. June 4, 2	2002-06-04
Method of forming ONO flash memory devices using rapid thermal oxidation Grant 6,395,654 - Yang , et al. May 28, 2	2002-05-28
Viable memory cell formed using rapid thermal annealing Grant 6,251,717 - Ramsbey , et al. June 26, 2	2001-06-26
Integrated method by using high temperature oxide for top oxide and periphery gate oxide Grant 6,117,730 - Komori , et al. September 12, 2	2000-09-12
Methods and arrangements for introducing nitrogen into a tunnel oxide in a non-volatile semiconductor memory device Grant 5,972,751 - Ramsbey , et al. October 26, 1	1999-10-26
Process for fabricating an integrated circuit with a self-aligned contact Grant 5,907,781 - Chen , et al. May 25, 1	1999-05-25

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.