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Patent applications and USPTO patent grants for Ramey; Carl G..The latest application filed is for "high performance, scalable multi chip interconnect".
Patent | Date |
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High performance, scalable multi chip interconnect Grant 10,887,238 - Ramey , et al. January 5, 2 | 2021-01-05 |
High Performance, Scalable Multi Chip Interconnect App 20200177510 - Ramey; Carl G. ;   et al. | 2020-06-04 |
Computing in parallel processing environments Grant 10,521,357 - Ramey , et al. Dec | 2019-12-31 |
Implementing hierarchical PCI express switch topology over coherent mesh interconnect Grant 10,394,747 - Paneah , et al. A | 2019-08-27 |
High performance, scalable multi chip interconnect Grant 10,367,741 - Ramey , et al. July 30, 2 | 2019-07-30 |
Computing in parallel processing environments Grant 10,360,168 - Griffin , et al. | 2019-07-23 |
Computing in parallel processing environments Grant 10,229,083 - Ramey | 2019-03-12 |
Managing cache access and streaming data Grant 10,210,092 - Miao , et al. Feb | 2019-02-19 |
Computing in parallel processing environments Grant 10,078,613 - Ramey September 18, 2 | 2018-09-18 |
Computing in parallel processing environments Grant 10,037,299 - Ramey , et al. July 31, 2 | 2018-07-31 |
Configurable device interfaces Grant 9,858,200 - Griffin , et al. January 2, 2 | 2018-01-02 |
Low latency dynamic route selection Grant 9,507,745 - Bratt , et al. November 29, 2 | 2016-11-29 |
Route prediction in packet switched networks Grant 9,479,431 - Bratt , et al. October 25, 2 | 2016-10-25 |
High performance, scalable multi chip interconnect Grant 9,424,228 - Ramey , et al. August 23, 2 | 2016-08-23 |
Managing cache access and streaming data Grant 9,213,652 - Miao , et al. December 15, 2 | 2015-12-15 |
Route prediction in packet switched networks Grant 9,135,215 - Bratt , et al. September 15, 2 | 2015-09-15 |
Low latency dynamic route selection Grant 8,934,347 - Bratt , et al. January 13, 2 | 2015-01-13 |
Configurable device interfaces Grant 8,799,624 - Griffin , et al. August 5, 2 | 2014-08-05 |
Computing in parallel processing environments Grant 8,738,860 - Griffin , et al. May 27, 2 | 2014-05-27 |
High Performance, Scalable Multi Chip Interconnect App 20140122560 - Ramey; Carl G. ;   et al. | 2014-05-01 |
Condensed router headers with low latency output port calculation Grant 8,572,353 - Bratt , et al. October 29, 2 | 2013-10-29 |
Managing home cache assignment Grant 8,539,155 - Miao , et al. September 17, 2 | 2013-09-17 |
Managing cache coherence Grant 8,521,963 - Miao , et al. August 27, 2 | 2013-08-27 |
Coupling data for interrupt processing in a parallel processing environment Grant 8,190,855 - Ramey , et al. May 29, 2 | 2012-05-29 |
Coupling data in a parallel processing environment Grant 7,636,835 - Ramey , et al. December 22, 2 | 2009-12-22 |
Coupling integrated circuits in a parallel processing environment Grant 7,539,845 - Wentzlaff , et al. May 26, 2 | 2009-05-26 |
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