loadpatents
name:-0.041630983352661
name:-0.052958011627197
name:-0.0081729888916016
Ramalingam; Suresh Patent Filings

Ramalingam; Suresh

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ramalingam; Suresh.The latest application filed is for "modular stacked silicon package assembly".

Company Profile
7.53.33
  • Ramalingam; Suresh - Fremont CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Thermal heat spreader plate for electronic device
Grant 11,373,929 - Refai-Ahmed , et al. June 28, 2
2022-06-28
Package integration for laterally mounted IC dies with dissimilar solder interconnects
Grant 11,373,989 - Gandhi , et al. June 28, 2
2022-06-28
Stacked silicon package assembly having thermal management
Grant 11,355,412 - Gandhi , et al. June 7, 2
2022-06-07
Force balanced package mounting
Grant 11,330,738 - Refai-Ahmed , et al. May 10, 2
2022-05-10
Three-dimensional thermal management apparatuses for electronic devices
Grant 11,328,976 - Refai-Ahmed , et al. May 10, 2
2022-05-10
Chip package assembly with enhanced solder resist crack resistance
Grant 11,315,858 - Sun , et al. April 26, 2
2022-04-26
Modular stacked silicon package assembly
Grant 11,302,674 - Gandhi , et al. April 12, 2
2022-04-12
Chip package assembly with stress decoupled interconnect layer
Grant 11,282,775 - Gandhi , et al. March 22, 2
2022-03-22
Micro device with through PCB cooling
Grant 11,246,211 - Refai-Ahmed , et al. February 8, 2
2022-02-08
Chip package assembly with enhanced interconnects and method for fabricating the same
Grant 11,217,550 - Gandhi , et al. January 4, 2
2022-01-04
Stacked silicon package assembly having thermal management using phase change material
Grant 11,195,780 - Gandhi , et al. December 7, 2
2021-12-07
Modular Stacked Silicon Package Assembly
App 20210366873 - GANDHI; Jaspreet Singh ;   et al.
2021-11-25
Stacked silicon package assembly having thermal management
Grant 11,145,566 - Refai-Ahmed , et al. October 12, 2
2021-10-12
Heterogeneous Integration Module Comprising Thermal Management Apparatus
App 20210305127 - REFAI-AHMED; Gamal ;   et al.
2021-09-30
Integrated electrical/optical interface with two-tiered packaging
Grant 11,107,770 - Ramalingam , et al. August 31, 2
2021-08-31
Stacked Silicon Package Assembly Having Thermal Management
App 20210249328 - REFAI-AHMED; Gamal ;   et al.
2021-08-12
Stacked Silicon Package Assembly Having Vertical Thermal Management
App 20210193620 - Refai-Ahmed; Gamal ;   et al.
2021-06-24
Method and apparatus of package enabled ESD protection
Grant 11,043,484 - Shi , et al. June 22, 2
2021-06-22
Fanout Integration For Stacked Silicon Package Assembly
App 20210134757 - GANDHI; Jaspreet Singh ;   et al.
2021-05-06
Chip scale package (CSP) including shim die
Grant 10,770,364 - Shi , et al. Sep
2020-09-08
Electronic device apparatus with multiple thermally conductive paths for heat dissipation
Grant 10,720,377 - Refai-Ahmed , et al.
2020-07-21
Electronic Device Apparatus With Multiple Thermally Conductive Paths For Heat Dissipation
App 20200152546 - Refai-Ahmed; Gamal ;   et al.
2020-05-14
Integrated circuit die with in-chip heat sink
Grant 10,629,512 - Pan , et al.
2020-04-21
Stacked Silicon Package Assembly Having Thermal Management
App 20200105642 - Gandhi; Jaspreet Singh ;   et al.
2020-04-02
Methods of interconnect for high density 2.5D and 3D integration
Grant 10,593,638 - Gandhi , et al.
2020-03-17
Chip Package Assembly With Enhanced Interconnects And Method For Fabricating The Same
App 20200035635 - Gandhi; Jaspreet Singh ;   et al.
2020-01-30
Testing system for lid-less integrated circuit packages
Grant 10,527,670 - Refai-Ahmed , et al. J
2020-01-07
Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management
Grant 10,529,645 - Gandhi , et al. J
2020-01-07
Integrated Circuit Die With In-chip Heat Sink
App 20200006186 - Pan; Hong-Tsz ;   et al.
2020-01-02
Multi-chip silicon substrate-less chip packaging
Grant 10,468,351 - Kwon , et al. No
2019-11-05
Chip Scale Package (csp) Including Shim Die
App 20190318975 - Shi; Hong ;   et al.
2019-10-17
Chip package assembly with enhanced interconnects and method for fabricating the same
Grant 10,319,606 - Gandhi , et al.
2019-06-11
Stacked silicon package having a thermal capacitance element
Grant 10,262,920 - Refai-Ahmed , et al.
2019-04-16
Methods And Apparatus For Thermal Interface Material (tim) Bond Line Thickness (blt) Reduction And Tim Adhesion Enhancement For Efficient Thermal Management
App 20180358280 - Gandhi; Jaspreet Singh ;   et al.
2018-12-13
Dynamic mounting thermal management for devices on board
Grant 10,147,664 - Refai-Ahmed , et al. De
2018-12-04
Dynamic Mounting Thermal Management For Devices On Board
App 20180308783 - Refai-Ahmed; Gamal ;   et al.
2018-10-25
Method and apparatus for assembling and testing a multi-integrated circuit package
Grant 10,096,502 - Refai-Ahmed , et al. October 9, 2
2018-10-09
Methods Of Interconnect For High Density 2.5d And 3d Integration
App 20180286826 - Gandhi; Jaspreet Singh ;   et al.
2018-10-04
Testing System For Lid-less Integrated Circuit Packages
App 20180284187 - Refai-Ahmed; Gamal ;   et al.
2018-10-04
Stacked silicon package assembly having an enhanced lid
Grant 10,043,730 - Refai-Ahmed , et al. August 7, 2
2018-08-07
Low insertion loss package pin structure and method
Grant 10,038,259 - Wu , et al. July 31, 2
2018-07-31
Method And Apparatus For Assembling And Testing A Multi-integrated Circuit Package
App 20180144963 - Refai-Ahmed; Gamal ;   et al.
2018-05-24
Techniques for molded underfill for integrated circuit dies
Grant 9,831,104 - Kwon , et al. November 28, 2
2017-11-28
Thermal management device with textured surface for extended cooling limit
Grant 9,812,374 - Refai-Ahmed , et al. November 7, 2
2017-11-07
Interposer with edge reinforcement and method for manufacturing same
Grant 9,627,329 - Kwon , et al. April 18, 2
2017-04-18
Stacked Silicon Package Assembly Having An Enhanced Lid
App 20170092619 - Refai-Ahmed; Gamal ;   et al.
2017-03-30
Methods for flip chip stacking
Grant 9,508,563 - Kwon , et al. November 29, 2
2016-11-29
Semiconductor assembly having bridge module for die-to-die interconnection
Grant 9,418,966 - Kwon , et al. August 16, 2
2016-08-16
Multi-chip Silicon Substrate-less Chip Packaging
App 20160064328 - Kwon; Woon-Seong ;   et al.
2016-03-03
Integrated circuit package with multi-trench structure on flipped substrate contacting underfill
Grant 9,245,865 - Kwon , et al. January 26, 2
2016-01-26
Through-silicon vias with metal system fill
Grant 9,236,341 - Kim , et al. January 12, 2
2016-01-12
Multi-die integrated circuits implemented using spacer dies
Grant 9,224,697 - Kwon , et al. December 29, 2
2015-12-29
Solder bump structure with enhanced high temperature aging reliability and method for manufacturing same
Grant 9,147,661 - Kwon , et al. September 29, 2
2015-09-29
Warpage management for fan-out mold packaged integrated circuit
Grant 9,006,030 - Kwon , et al. April 14, 2
2015-04-14
Substrate-less interposer technology for a stacked silicon interconnect technology (SSIT) product
Grant 8,946,884 - Kwon , et al. February 3, 2
2015-02-03
Multi-layer Core Organic Package Substrate
App 20140262440 - Kim; Namhoon ;   et al.
2014-09-18
Substrate-less Interposer Technology For A Stacked Silicon Interconnect Technology (ssit) Product
App 20140252599 - Kwon; Woon-Seong ;   et al.
2014-09-11
Methods For Flip Chip Stacking
App 20140017852 - Kwon; Woon-Seong ;   et al.
2014-01-16
Methods for flip chip stacking
Grant 8,618,648 - Kwon , et al. December 31, 2
2013-12-31
Process for assembling an integrated circuit package having a substrate vent hole
Grant RE44,629 - Ramalingam , et al. December 10, 2
2013-12-10
Integrated Circuit Connectivity Using Flexible Circuitry
App 20130181360 - Kim; Namhoon ;   et al.
2013-07-18
Through-silicon Vias With Low Parasitic Capacitance
App 20110291287 - Wu; Paul Y. ;   et al.
2011-12-01
Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials
Grant 7,141,448 - Ramalingam , et al. November 28, 2
2006-11-28
Optical subassembly
Grant 7,066,657 - Murali , et al. June 27, 2
2006-06-27
Optical Subassembly
App 20050117853 - Murali, Venkatesan ;   et al.
2005-06-02
Optic switch
Grant 6,778,727 - Ramalingam , et al. August 17, 2
2004-08-17
Optic switch
App 20040096144 - Ramalingam, Suresh ;   et al.
2004-05-20
Compact, low insertion loss, high yield arrayed waveguide grating
Grant 6,697,553 - Bhardwaj , et al. February 24, 2
2004-02-24
Optic switch
Grant 6,687,427 - Ramalingam , et al. February 3, 2
2004-02-03
Package for optical components
Grant 6,664,511 - Crafts , et al. December 16, 2
2003-12-16
Compact, low insertion loss, high yield arrayed waveguide grating
App 20030156789 - Bhardwaj, Jyoti Kiron ;   et al.
2003-08-21
Transfer molded packages with embedded thermal insulation
Grant 6,606,425 - Crafts , et al. August 12, 2
2003-08-12
Package for optical components
App 20030085212 - Crafts, Douglas E. ;   et al.
2003-05-08
Redundant Package For Optical Components
App 20030006224 - Crafts, Douglas E. ;   et al.
2003-01-09
Integrated circuit package having a substrate vent hole
Grant 6,490,166 - Ramalingam , et al. December 3, 2
2002-12-03
Redundant package for optical components
Grant 6,486,440 - Crafts , et al. November 26, 2
2002-11-26
High performance via capacitor and method for manufacturing same
App 20020085336 - Winer, Paul ;   et al.
2002-07-04
Optic switch
App 20020085788 - Ramalingam, Suresh ;   et al.
2002-07-04
Controlled collapse chip connection (C4) integrated circuit package which has two dissimilar underfill materials
App 20020017728 - Ramalingam, Suresh ;   et al.
2002-02-14
Controlled Collapse Chip Connection (c4) Integrated Circuit Package Which Has Two Dissimilar Underfill Materials
App 20020014688 - RAMALINGAM, SURESH ;   et al.
2002-02-07

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