Ramalingam; Shyam

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ramalingam; Shyam.The latest application filed is for "conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and metho".

Company Profile

2.12.12

Ramalingam; Shyam - Boise ID
Ramalingam, Shyam - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods Grant 11,011,420 - Li , et al. May 18, 2	2021-05-18
Interconnect assemblies with through-silicon vias and stress-relief features Grant 10,847,442 - Li , et al. November 24, 2	2020-11-24
Conductive Interconnect Structures Incorporating Negative Thermal Expansion Materials And Associated Systems, Devices, And Metho App 20200235007 - Li; Hongqi ; et al.	2020-07-23
Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods Grant 10,546,777 - Li , et al. Ja	2020-01-28
Capping poly channel pillars in stacked circuits Grant 10,319,678 - Li , et al.	2019-06-11
Conductive Interconnect Structures Incorporating Negative Thermal Expansion Materials And Associated Systems, Devices, And Methods App 20180174902 - Li; Hongqi ; et al.	2018-06-21
Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods Grant 9,922,875 - Li , et al. March 20, 2	2018-03-20
Semiconductor constructions and methods of forming intersecting lines of material Grant 9,911,643 - Li , et al. March 6, 2	2018-03-06
Conductive Interconnect Structures Incorporating Negative Thermal Expansion Materials And Associated Systems, Devices, And Methods App 20170316974 - Li; Hongqi ; et al.	2017-11-02
Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods Grant 9,754,825 - Li , et al. September 5, 2	2017-09-05
Method For Forming A Metal Cap In A Semiconductor Memory Device App 20170133585 - Balakrishnan; Muralikrishnan ; et al.	2017-05-11
Method for forming a metal cap in a semiconductor memory device Grant 9,577,192 - Balakrishnan , et al. February 21, 2	2017-02-21
Semiconductor Constructions and Methods of Forming Intersecting Lines of Material App 20160293482 - Li; Hongqi ; et al.	2016-10-06
Capping Poly Channel Pillars In Stacked Circuits App 20160247756 - Li; Hongqi ; et al.	2016-08-25
Semiconductor constructions Grant 9,391,001 - Li , et al. July 12, 2	2016-07-12
Capping poly channel pillars in stacked circuits Grant 9,263,459 - Li , et al. February 16, 2	2016-02-16
Conductive Interconnect Structures Incorporating Negative Thermal Expansion Materials And Associated Systmes, Devices, And Methods App 20150340282 - Li; Hongqi ; et al.	2015-11-26
Method For Forming A Metal Cap In A Semiconductor Memory Device App 20150340247 - Balakrishnan; Muralikrishnan ; et al.	2015-11-26
Interconnect Assemblies With Through-silicon Vias And Stress-relief Features App 20150243583 - Li; Hongqi ; et al.	2015-08-27
Conductive interconnect structures incorporating negative thermal expansion materials and associated systems, devices, and methods Grant 9,099,442 - Li , et al. August 4, 2	2015-08-04
Semiconductor Constructions App 20150054164 - Li; Hongqi ; et al.	2015-02-26
Conductive Interconnect Structures Incorporating Negative Thermal Expansion Materials And Associated Systems, Devices, And Methods App 20150035150 - Li; Hongqi ; et al.	2015-02-05
Selective etch of films with high dielectric constant App 20050153563 - Ramalingam, Shyam ; et al.	2005-07-14

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