loadpatents
name:-0.014139890670776
name:-0.011618137359619
name:-0.00043892860412598
Rakshani; Vafa J. Patent Filings

Rakshani; Vafa J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rakshani; Vafa J..The latest application filed is for "memory cell for modification of revision identifier in an integrated circuit chip".

Company Profile
0.7.7
  • Rakshani; Vafa J. - Newport Coast CA US
  • Rakshani; Vafa J - Newport Coast CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and system for advance high performance bus synchronizer
Grant 8,989,331 - Liu , et al. March 24, 2
2015-03-24
Memory cell for modification of revision identifier in an integrated circuit chip
Grant 8,299,503 - Catalasan , et al. October 30, 2
2012-10-30
Programmable memory cell in an integrated circuit chip
Grant 7,768,037 - Catalasan , et al. August 3, 2
2010-08-03
Memory Cell For Modification of Revision Identifier In An Integrated Circuit Chip
App 20100187574 - Catalasan; Manolito M. ;   et al.
2010-07-29
Method for manufacturing a memory cell for modification of revision identifier in an integrated circuit chip
Grant 7,341,891 - Catalasan , et al. March 11, 2
2008-03-11
Method and system for advance high performance bus synchronizer
App 20070280396 - Liu; Sam H. ;   et al.
2007-12-06
Programmable memory cell in an integrated circuit chip
App 20070131966 - Catalasan; Manolito M. ;   et al.
2007-06-14
Coupling of signals between adjacent functional blocks in an integrated circuit chip
Grant 7,078,936 - Catalasan , et al. July 18, 2
2006-07-18
Memory cell for modification of default register values in an integrated circuit chip
Grant 6,933,547 - Catalasan , et al. August 23, 2
2005-08-23
Memory cell for modification of revision identifier in an integrated circuit chip
App 20040251472 - Catalasan, Manolito M. ;   et al.
2004-12-16
Coupling of signals between adjacent functional blocks in an integrated circuit chip
App 20040251501 - Catalasan, Manolito M. ;   et al.
2004-12-16
Method for manufacturing a memory cell for modification of revision identifier in an integrated circuit chip
App 20040253778 - Catalasan, Manolito M. ;   et al.
2004-12-16
Memory Cell For Modification Of Default Register Values In An Integrated Circuit Chip
App 20040251470 - Catalasan, Manolito M. ;   et al.
2004-12-16

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