Rajan; Suresh N.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rajan; Suresh N..The latest application filed is for "error correction in a memory device".

Company Profile

2.9.17

Rajan; Suresh N. - Fremont CA
Rajan; Suresh N. - San Jose CA
- San Jose CA US
Rajan; Suresh N. - US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Error correction in a memory device Grant 9,575,835 - Vogelsang , et al. February 21, 2	2017-02-21
Error Correction In A Memory Device App 20150234707 - Vogelsang; Thomas ; et al.	2015-08-20
Error correction in a memory device Grant 9,037,949 - Vogelsang , et al. May 19, 2	2015-05-19
Methods and apparatus of stacking DRAMs Grant 8,619,452 - Rajan , et al. December 31, 2	2013-12-31
Methods and apparatus of stacking DRAMs Grant 08619452 -	2013-12-31
Memory Module With Memory Stack And Interface With Enhanced Capabilites App 20130103896 - Rajan; Suresh N. ; et al.	2013-04-25
Methods And Apparatus Of Stacking Drams App 20130100746 - Rajan; Suresh N. ; et al.	2013-04-25
Methods And Apparatus Of Stacking Drams App 20120268982 - Rajan; Suresh N.	2012-10-25
Memory Module With Memory Stack And Interface With Enhanced Capabilities App 20120102292 - Rajan; Suresh N. ; et al.	2012-04-26
Memory module with memory stack and interface with enhanced capabilities Grant 8,089,795 - Rajan , et al. January 3, 2	2012-01-03
Method and Circuit for Configuring Memory Core Integrated Circuit Dies with Memory Interface Integrated Circuit Dies App 20110310686 - Rajan; Suresh N.	2011-12-22
Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies Grant 7,990,746 - Rajan August 2, 2	2011-08-02
Methods And Apparatus Of Stacking Drams App 20100020585 - Rajan; Suresh N.	2010-01-28
Method And Circuit For Configuring Memory Core Integrated Circuit Dies With Memory Interface Integrated Circuit Dies App 20090290442 - Rajan; Suresh N.	2009-11-26
Methods and apparatus of stacking DRAMs Grant 7,599,205 - Rajan October 6, 2	2009-10-06
Integrated memory core and memory interface circuit Grant 7,515,453 - Rajan April 7, 2	2009-04-07
Methods And Apparatus Of Stacking Drams App 20080170425 - Rajan; Suresh N.	2008-07-17
Memory module with memory stack App 20080126690 - Rajan; Suresh N. ; et al.	2008-05-29
Methods and apparatus of stacking DRAMs Grant 7,379,316 - Rajan May 27, 2	2008-05-27
Memory module with memory stack and interface with enhanced capabilities App 20070195613 - Rajan; Suresh N. ; et al.	2007-08-23
Methods and apparatus of stacking DRAMs App 20070058471 - Rajan; Suresh N. ; et al.	2007-03-15
Methods and apparatus of stacking DRAMs App 20070058410 - Rajan; Suresh N.	2007-03-15
Integrated memory core and memory interface circuit App 20070050530 - Rajan; Suresh N.	2007-03-01
Method and circuit for configuring memory core integrated circuit dies with memory interface integrated circuit dies App 20070014168 - Rajan; Suresh N.	2007-01-18

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