Rajagopalan; Vidya

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rajagopalan; Vidya.The latest application filed is for "data cache virtual hint way prediction, and applications thereof".

Company Profile

0.11.7

Rajagopalan; Vidya - Palo Alto CA
Rajagopalan; Vidya - San Carlos CA
Rajagopalan; Vidya - Hudson MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Data Cache Virtual Hint Way Prediction, And Applications Thereof App 20150293853 - Yu; Meng-Bing ; et al.	2015-10-15
Data cache virtual hint way prediction, and applications thereof Grant 9,092,343 - Yu , et al. July 28, 2	2015-07-28
Conditional move instruction formed into one decoded instruction to be graduated and another decoded instruction to be invalidated Grant 8,078,846 - Kishore , et al. December 13, 2	2011-12-13
Conditional branch execution in a processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses Grant 7,721,075 - Thekkath , et al. May 18, 2	2010-05-18
Processor core and method for managing branch misprediction in an out-of-order processor pipeline Grant 7,711,934 - Kishore , et al. May 4, 2	2010-05-04
Data Cache Virtual Hint Way Prediction, and Applications Thereof App 20100011166 - YU; Meng-Bing ; et al.	2010-01-14
Data cache virtual hint way prediction, and applications thereof Grant 7,594,079 - Yu , et al. September 22, 2	2009-09-22
Twice issued conditional move instruction, and applications thereof App 20080082795 - Kishore; Karagada Ramarao ; et al.	2008-04-03
Data cache virtual hint way prediction, and applications thereof App 20080082721 - Yu; Meng-Bing ; et al.	2008-04-03
Processor having a write-tie instruction and a data mover engine that associates register addresses with memory addresses App 20070174595 - Thekkath; Radhika ; et al.	2007-07-26
Processor core and method for managing branch misprediction in an out-of-order processor pipeline App 20070101110 - Kishore; Karagada Ramarao ; et al.	2007-05-03
Apparatus And Method To Trace High Performance Multi-issue Processors App 20070089095 - Thekkath; Radhika ; et al.	2007-04-19
System and method to trace high performance multi-issue processors Grant 7,159,101 - Thekkath , et al. January 2, 2	2007-01-02
Program counter and data tracing from a multi-issue processor Grant 7,124,072 - Thekkath , et al. October 17, 2	2006-10-17
Low latency system bus interface for multi-master processing environments Grant 6,732,208 - Alsaadi , et al. May 4, 2	2004-05-04
Scalable on-chip system bus Grant 6,493,776 - Courtright , et al. December 10, 2	2002-12-10
Method and apparatus for controlling a rounding operation in a floating point multiplier circuit Grant 5,341,319 - Madden , et al. August 23, 1	1994-08-23

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