Rainey; BethAnn
Patent Applications and Registrations
Patent applications and USPTO patent grants for Rainey; BethAnn.The latest application filed is for "noble gas implantation region in top silicon layer of semiconductor-on-insulator substrate".
Company Profile
0.26.25
- Rainey; BethAnn - Williston VT
- Rainey; BethAnn - Essex Junction NY
- Rainey; BethAnn - South Burlington VT
- Rainey; BethAnn - Burlington VT
Patent Activity
| Patent | Date |
|---|---|
| Flattened substrate surface for substrate bonding Grant 8,778,737 - Cooney, III , et al. July 15, 2 | 2014-07-15 |
| Noble gas implantation region in top silicon layer of semiconductor-on-insulator substrate Grant 8,748,285 - Botula , et al. June 10, 2 | 2014-06-10 |
| Noble Gas Implantation Region In Top Silicon Layer Of Semiconductor-on-insulator Substrate App 20130134518 - Botula; Alan B. ; et al. | 2013-05-30 |
| Flattened Substrate Surface For Substrate Bonding App 20130105981 - Cooney, III; Edward C. ; et al. | 2013-05-02 |
| Integration of multiple gate oxides with shallow trench isolation methods to minimize divot formation Grant 8,227,318 - Levy , et al. July 24, 2 | 2012-07-24 |
| Simultaneously formed isolation trench and through-box contact for silicon-on-insulator technology Grant 8,021,943 - Botula , et al. September 20, 2 | 2011-09-20 |
| FinFET transistor and circuit Grant 7,964,466 - Bernstein , et al. June 21, 2 | 2011-06-21 |
| Simultaneously Formed Isolation Trench And Through-box Contact For Silicon-on-insulator Technology App 20110124177 - Botula; Alan B. ; et al. | 2011-05-26 |
| Integration of Multiple Gate Oxides with Shallow Trench Isolation Methods to Minimize Divot Formation App 20110117714 - Levy; Max ; et al. | 2011-05-19 |
| Structures including means for lateral current carrying capability improvement in semiconductor devices Grant 7,904,868 - Feilchenfeld , et al. March 8, 2 | 2011-03-08 |
| Selectable device options for characterizing semiconductor devices Grant 7,814,454 - Chou , et al. October 12, 2 | 2010-10-12 |
| FinFET transistor and circuit Grant 7,777,276 - Bernstein , et al. August 17, 2 | 2010-08-17 |
| finFET TRANSISTOR AND CIRCUIT App 20100203689 - Bernstein; Kerry ; et al. | 2010-08-12 |
| Semiconductor device having freestanding semiconductor layer Grant 7,709,892 - Anderson , et al. May 4, 2 | 2010-05-04 |
| Virtual body-contacted trigate Grant 7,700,446 - Anderson , et al. April 20, 2 | 2010-04-20 |
| Design Structures Including Means For Lateral Current Carrying Capability Improvement In Semiconductor Devices App 20090106726 - Feilchenfeld; Natalie Barbara ; et al. | 2009-04-23 |
| Selectable Device Options For Characterizing Semiconductor Devices App 20090007051 - Chou; Anthony I. ; et al. | 2009-01-01 |
| Method of making a finFET having suppressed parasitic device characteristics Grant 7,470,578 - Nowak , et al. December 30, 2 | 2008-12-30 |
| Lateral Current Carrying Capability Improvement In Semiconductor Devices App 20080308940 - Feilchenfeld; Natalie Barbara ; et al. | 2008-12-18 |
| Methods for lateral current carrying capability improvement in semiconductor devices Grant 7,453,151 - Feilchenfeld , et al. November 18, 2 | 2008-11-18 |
| METHODS OF BASE FORMATION IN A BiCMOS PROCESS App 20080268604 - Geiss; Peter J. ; et al. | 2008-10-30 |
| Methods of base formation in a BiCMOS process Grant 7,390,721 - Geiss , et al. June 24, 2 | 2008-06-24 |
| Methods For Lateral Current Carrying Capability Improvement In Semiconductor Devices App 20080122096 - Feilchenfeld; Natalie Barbara ; et al. | 2008-05-29 |
| FinFET transistor and circuit Grant 7,368,355 - Bernstein , et al. May 6, 2 | 2008-05-06 |
| FinFET TRANSISTOR AND CIRCUIT App 20080099795 - Bernstein; Kerry ; et al. | 2008-05-01 |
| Virtual body-contacted trigate Grant 7,288,802 - Anderson , et al. October 30, 2 | 2007-10-30 |
| Virtual Body-contacted Trigate App 20070023756 - Anderson; Brent A. ; et al. | 2007-02-01 |
| FinFET TRANSISTOR AND CIRCUIT App 20060255410 - Bernstein; Kerry ; et al. | 2006-11-16 |
| FinFET transistor and circuit Grant 7,115,920 - Bernstein , et al. October 3, 2 | 2006-10-03 |
| Method of forming freestanding semiconductor layer Grant 7,087,506 - Anderson , et al. August 8, 2 | 2006-08-08 |
| Method of making a finFET having suppressed parasitic device characteristics App 20060057802 - Nowak; Edward J. ; et al. | 2006-03-16 |
| FinFET having suppressed parasitic device characteristics Grant 6,992,354 - Nowak , et al. January 31, 2 | 2006-01-31 |
| Methods of base formation in a BiCMOS process App 20060017066 - Geiss; Peter J. ; et al. | 2006-01-26 |
| Method of base formation in a BiCMOS process Grant 6,965,133 - Geiss , et al. November 15, 2 | 2005-11-15 |
| FinFET transistor and circuit App 20050224890 - Bernstein, Kerry ; et al. | 2005-10-13 |
| High-density split-gate FinFET Grant 6,953,726 - Nowak , et al. October 11, 2 | 2005-10-11 |
| Method Of Base Formation In A Bicmos Process App 20050199908 - Geiss, Peter J. ; et al. | 2005-09-15 |
| Multi-height FinFETS Grant 6,909,147 - Aller , et al. June 21, 2 | 2005-06-21 |
| High-density split-gate FinFET App 20050104130 - Nowak, Edward J. ; et al. | 2005-05-19 |
| High-density split-gate FinFET Grant 6,888,199 - Nowak , et al. May 3, 2 | 2005-05-03 |
| High-density Split-gate Finfet App 20050073005 - Nowak, Edward J. ; et al. | 2005-04-07 |
| Self-aligned raised extrinsic base bipolar transistor structure and method Grant 6,869,852 - Joseph , et al. March 22, 2 | 2005-03-22 |
| Method Of Forming Freestanding Semiconductor Layer App 20050009305 - Anderson, Brent A ; et al. | 2005-01-13 |
| METHOD OF MAKING A finFET HAVING SUPPRESSED PARASITIC DEVICE CHARACTERISTICS App 20040262688 - Nowak, Edward J. ; et al. | 2004-12-30 |
| Multi-height Finfets App 20040222477 - Aller, Ingo ; et al. | 2004-11-11 |
| High mobility crystalline planes in double-gate CMOS technology Grant 6,794,718 - Nowak , et al. September 21, 2 | 2004-09-21 |
| Dense Dual-plane Devices App 20040119100 - Nowak, Edward J. ; et al. | 2004-06-24 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 