Rahut; Anirban

Patent Applications and Registrations

Patent applications and USPTO patent grants for Rahut; Anirban.The latest application filed is for "search result replication management in a search head cluster".

Company Profile

1.22.5

Rahut; Anirban - Santa Clara CA
Rahut; Anirban - Sunnyvale CA
Rahut; Anirban - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High availability scheduler for scheduling map-reduce searches based on a leader state Grant 10,698,777 - Rahut	2020-06-30
Search Result Replication Management In A Search Head Cluster App 20190073409 - Rahut; Anirban ; et al.	2019-03-07
Search result replication in a search head cluster Grant 10,133,806 - Rahut , et al. November 20, 2	2018-11-20
High Availability Scheduler For Scheduling Map-reduce Searches App 20180300209 - Rahut; Anirban	2018-10-18
High availability scheduler for scheduling searches of time stamped events Grant 9,983,954 - Rahut May 29, 2	2018-05-29
High Availability Scheduler For Scheduling Searches Of Time Stamped Events App 20160117230 - Rahut; Anirban	2016-04-28
High availability scheduler for scheduling map-reduce searches Grant 9,256,501 - Rahut February 9, 2	2016-02-09
Search Result Replication In A Search Head Cluster App 20160034555 - Rahut; Anirban ; et al.	2016-02-04
High Availability Scheduler For Scheduling Map-reduce Searches App 20160034566 - Rahut; Anirban	2016-02-04
High availability scheduler Grant 9,047,246 - Rahut June 2, 2	2015-06-02
Latch based optimization during implementation of circuit designs for programmable logic devices Grant 8,146,041 - Srinivasan , et al. March 27, 2	2012-03-27
Run-time efficient methods for routing large multi-fanout nets Grant 8,015,535 - Kong , et al. September 6, 2	2011-09-06
Latch based optimization during implementation of circuit designs for programmable logic devices Grant 8,010,923 - Srinivasan , et al. August 30, 2	2011-08-30
Method and apparatus for selecting programmable interconnects to reduce clock skew Grant 7,904,860 - Rahut March 8, 2	2011-03-08
Patterns for routing nets in a programmable logic device Grant 7,797,665 - Xu , et al. September 14, 2	2010-09-14
Methods of estimating net delays in tile-based PLD architectures Grant 7,735,039 - Dasasathyan , et al. June 8, 2	2010-06-08
Method and apparatus for facilitating signal routing within a programmable logic device Grant 7,725,868 - Verma , et al. May 25, 2	2010-05-25
Run-time efficient methods for routing large multi-fanout nets Grant 7,620,923 - Kong , et al. November 17, 2	2009-11-17
Method and apparatus for selecting programmable interconnects to reduce clock skew Grant 7,430,728 - Rahut September 30, 2	2008-09-30
Assigning inputs of look-up tables to improve a design implementation in a programmable logic device Grant 7,424,697 - Arslan , et al. September 9, 2	2008-09-09
Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures Grant 7,389,485 - Rahut , et al. June 17, 2	2008-06-17
Run-time efficient methods for routing large multi-fanout nets Grant 7,376,926 - Kong , et al. May 20, 2	2008-05-20
Method and apparatus for facilitating signal routing within a programmable logic device Grant 7,306,977 - Verma , et al. December 11, 2	2007-12-11
Using router feedback for placement improvements for logic design Grant 7,076,758 - Srinivasan , et al. July 11, 2	2006-07-11
Upper-bound calculation for placed circuit design performance Grant 7,051,312 - Rahut , et al. May 23, 2	2006-05-23
Method and apparatus for selecting programmable interconnects to reduce clock skew Grant 6,952,813 - Rahut October 4, 2	2005-10-04
Interconnect routing using logic levels Grant 6,766,504 - Rahut , et al. July 20, 2	2004-07-20

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